My ARM board doesn't have SRST wired up, so I am using a software reset (watchdog timer).
This works most of the time but just failed with the core in "Abort" mode, and immediately after I got a lot of "Address translation failure". Is there something I should do in my software reset routine to make it more robust? Explicitly set the processor mode perhaps? I looked in the docs but couldn't see how to do that. My reset routine just calls "halt" at the moment then starts trying to set the WDT with "mww phys" calls. Some output when things went wrong: watchdog_reset called target state: halted target halted in ARM state due to debug-request, current mode: Abort cpsr: 0x200000d7 pc: 0xffff000c MMU: enabled, D-Cache: enabled, I-Cache: enabled watchdog_reset done target state: halted target halted in ARM state due to debug-request, current mode: Abort cpsr: 0x200000d7 pc: 0xffff035c MMU: enabled, D-Cache: enabled, I-Cache: enabled Initialize Video VBOX RCLK not supported - fallback to 1000 kHz Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure Address translation failure When things go right (although the pc usually shows 0x20, not sure what happened this time..) watchdog_reset called target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x80000013 pc: 0x00009860 MMU: disabled, D-Cache: disabled, I-Cache: disabled watchdog_reset done target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x80000013 pc: 0x00009bb0 MMU: disabled, D-Cache: disabled, I-Cache: disabled -- Jon Povey jon.po...@racelogic.co.uk Racelogic is a limited company registered in England. Registered number 2743719 . Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB . The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
