Signed-off-by: Øyvind Harboe <oyvind.har...@zylin.com>
---
src/target/arm_adi_v5.c | 20 +++++++++++++++-----
src/target/cortex_m3.c | 44 +++++++++++++++++++++++++++++++++-----------
2 files changed, 48 insertions(+), 16 deletions(-)
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 9a33d82..496360f 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1088,11 +1088,21 @@ static int dap_info_command(struct command_context
*cmd_ctx,
command_print(cmd_ctx, "\tROM table in legacy format");
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec
*/
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0,
&cid0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4,
&cid1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8,
&cid2);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC,
&cid3);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC,
&memtype);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index d6090f5..6939890 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -68,7 +68,9 @@ static int cortexm3_dap_read_coreregister_u32(struct
adiv5_dap *swjdp,
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
- mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
DCB_DCRSR & 0xFFFFFFF0);
@@ -107,7 +109,9 @@ static int cortexm3_dap_write_coreregister_u32(struct
adiv5_dap *swjdp,
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
- mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
DCB_DCRDR & 0xFFFFFFF0);
@@ -297,33 +301,51 @@ static int cortex_m3_examine_exception_reason(struct
target *target)
struct adiv5_dap *swjdp = &armv7m->dap;
int retval;
- mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+ retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+ if (retval != ERROR_OK)
+ return retval;
switch (armv7m->exception_number)
{
case 2: /* NMI */
break;
case 3: /* Hard Fault */
- mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR,
&except_sr);
+ if (retval != ERROR_OK)
+ return retval;
if (except_sr & 0x40000000)
{
- mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR,
&cfsr);
+ if (retval != ERROR_OK)
+ return retval;
}
break;
case 4: /* Memory Management */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 5: /* Bus Fault */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 6: /* Usage Fault */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
- mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+ retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 14: /* PendSV */
break;
--
1.6.3.3
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