I have been able to run a similar function on the DM37x without halting
the processor. The DM37x is very similar to the OMAP. One thing I
noticed is that the write did not work when the processor was halted
unless I called "mww phys" to set DBGEN. For some reason just "mww" was
failing even if the MMU was not enabled.
Have you tried using a physical address write?
-Karl
On 09/24/2010 04:36 PM, Zachary T Welch wrote:
Without this patch, omap3_dbginit's attempt to set DBGEN will fail
when the CPU is running, and the debugger cannot halt the CPU without
that bit set. This patch does not need to be committed as-is; rather,
I want to know: how is it that no one else reported this issue?
What negative consequences can result from removing this check?
---
src/target/cortex_a8.c | 5 -----
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 8b4ced5..9e09ddb 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -2014,11 +2014,6 @@ static int cortex_a8_enable_mmu_caches(struct target
*target, int mmu,
static int cortex_a8_mmu(struct target *target, int *enabled)
{
- if (target->state != TARGET_HALTED) {
- LOG_ERROR("%s: target not halted", __func__);
- return ERROR_TARGET_INVALID;
- }
-
*enabled =
target_to_cortex_a8(target)->armv7a_common.armv4_5_mmu.mmu_enabled;
return ERROR_OK;
}
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