On Sat, Dec 11, 2010 at 5:43 AM, Antonio Borneo <borneo.anto...@gmail.com> wrote: > Hi Drasko, > your system has an ARM946E. Should have "vector_catch" capability. > Please check if command "arm9 vector_catch" shows the reset feature. > In such case, after set it to catch reset, you can press the reset > button to trigger OpenOCD and get CPU halted at first instruction. > > If everything works, then you can have a look at the file > tcl/chip/st/spear/quirk_no_srst.tcl > The file above is not specific for ST SPEAr, but today is tested and > used on such system only. > It uses vector_catch and integrates in OpenOCD reset command the > required functionality to catch the reset. > You could use similar stuff for your system too.
Hello Antonio, thank you very much for these instructions. I tried vector_catch feature, and it seem to work well, pressing the reset button now I get : target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x000000d3 pc: 0xffff0000 However, if I do reset write into SOC_RESET register, I am getting : target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x20000053 pc: 0x00811578 i.e. PC was stopped somewhere, and not at vector 0xffff0000. Do you have any idea why ? Best regards, Drasko _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
