Hello, sorry, the reset call doesnt work.
I can try it from my upload script (included in the cfg file) or from telnet. Openocd crash on both. I have also append the console output without the debug option. Regards, Mathias --- console output --- Open On-Chip Debugger 0.5.0-dev-00658-gaf3f77a (2010-12-17-07:26) Licensed under GNU GPL v2 For bug reports, read http://openocd.berlios.de/doc/doxygen/bugs.html Info : only one transport option; autoselect 'jtag' 600 kHz adapter_nsrst_delay: 100 jtag_ntrst_delay: 100 srst_only separate srst_gates_jtag srst_open_drain Warn : use 'lm3s3748.cpu' as target identifier, not '0' upload Info : clock speed 600 kHz Info : JTAG tap: lm3s3748.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3) Info : lm3s3748.cpu: hardware has 6 breakpoints, 4 watchpoints Info : accepting 'telnet' connection from 4444 Info : JTAG tap: lm3s3748.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3) <crash after reset command> --- Am 17.12.2010 11:14, schrieb Spencer Oliver: > On 17/12/2010 07:54, Mathias K. wrote: >> Hello, >> >> the command "soft_reset_halt" of the current git version of openocd segfault: >> >> >> (gdb) bt full >> #0 cortex_m3_assert_reset (target=0x818dba0) at cortex_m3.c:942 >> cortex_m3 = 0x818f118 >> swjdp = 0x818f1d0 >> reset_config =<error reading variable reset_config (Cannot access >> memory at address >> 0xefffffd9)> >> jtag_reset_config =<error reading variable jtag_reset_config >> (Cannot access memory at >> address 0xefffffdd)> >> retval =<value optimized out> >> __func__ = "cortex_m3_assert_reset" >> __FUNCTION__ = "cortex_m3_assert_reset" >> Cannot access memory at address 0xf0000005 >> >> > > Slightly confused as soft_reset_halt does not call assert_reset. > Can you show me the setup you are using? > > To be honest there is not really a need for a target soft_reset_halt on the > cortex as the normal > reset can perform the same thing. > > Cheers > Spen >
# Script for luminary lm3s3748 # # NB! work in progress! Duplicated from lm3s811.cfg, but does # it need modification?? if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME; } else { set _CHIPNAME lm3s3748 } if { [info exists ENDIAN] } { set _ENDIAN $ENDIAN } else { # this defaults to a little endian set _ENDIAN little } if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { # force an error till we get a good number set _CPUTAPID 0x3ba00477 } # jtag_khz 600 # jtag_nsrst_delay 100 jtag_ntrst_delay 100 #lm3s3748 Evaluation Board has only srst reset_config srst_only #jtag scan chain jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID # the luminary variant causes a software reset rather than asserting SRST # this stops the debug registers from being cleared # this will be fixed in later revisions of silicon set _TARGETNAME [format "%s.cpu" $_CHIPNAME] target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s # 8k working area at base of ram $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x8000 -work-area-backup 0 #flash configuration set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME stellaris 0 0 0 0 0 # # # proc upload { } { reset init sleep 10 halt sleep 10 #wait_halt flash probe 0 sleep 10 flash write_image erase uart_echo.bin sleep 10 #reset init halt sleep 10 gdb_breakpoint_override soft #soft_reset_halt reset run }
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