Hi Luca,
On 28/01/11 22:18, luca ellero wrote:
I think it would be easy to add a flag or similar to the memory dump
commands in OpenOCD to have the A9 issue memory accesses on behalf of
the debugger, so we can access resources on the L2 interconnect... it
is already like this on some CPUs. Not sure how useful it would be,
though.
Great idea, I think it would be very useful to examine what ROM code do!
I will investigate!
Great, keep us posted. Actually, this will definitely be generally
useful, because there are many other resources that can't be accessed
from the L3 interconnect: the MPCore private regions (per-core timers
and WDT), snoop-control unit, global interrupt controller, local PRCM,
and of course ROM. Any A9mp will have the same issue.
I wonder what the best way to is to implement this. One option could be
a table that maps address ranges to access methods. This would have to
be configured both cpu-cpu (e.g. Cortex-A9 per-core timers) and per-SoC
(e.g. OMAP4430 ROM). This would be almost totally transparent to the
user, but could be a configuration nightmare.
Otherwise it could be a flag to the various commands that specify the
access should be serviced by the cpu, rather than a direct access to the
host bus. Your thoughts?
PS. your x-loader patch works great! Now I can halt the processor even
after x-loader runs. How about sending the patch to x-loader guys?
Excellent, thanks for testing. I've sent the patch upstream.
Cheers,
-- Aaron
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