On Mon, Aug 1, 2011 at 9:45 PM, Eric Wetzel <thewet...@gmail.com> wrote:
> I did a rather tedious bisection on the J-Link firmwares released by
> Segger. Here is where the defect is introduced:
> V4.14h: Bad (tested) J-Link ARM V8 compiled Aug 4 2010 19:16:19
>
> The last good version was:
> V4.14g: Good (tested) J-Link ARM V8 compiled Dec 1 2009 11:42:48
>
> Their Release Notes aren't very consistent in these packages, being
> labeled "Release notes for J-Flash ARM V4.08a" and having version
> information only up until V4.12. But who knows what they could have
> changed in 8 months.
>
> And I tested the latest version (V4.32) to ensure that the problem
> wasn't corrected on their end, and it was not.
>
> I only tested this on my V8 J-Link, but Xiaofan said that the V7 works fine.
I just tried V6 and it seems to work as well.
SEGGER J-Link Commander V4.32 ('?' for help)
Compiled Jul 29 2011 18:38:14
DLL version V4.32, compiled Jul 29 2011 18:37:55
Firmware: J-Link ARM V6 compiled Feb 1 2011 14:28:14
Hardware: V6.00
S/N: xxxxxxxxxx
OEM: IAR
J-Link>f
Firmware: J-Link ARM V6 compiled Feb 1 2011 14:28:14
Hardware: V6.00
J-Link>st
VTarget=3.274V
ITarget=109mA
TCK=1 TDI=0 TDO=1 TMS=0 TRES=1 TRST=1
Supported JTAG speeds:
- 48 MHz/n, (n>=4). => 12000kHz, 9600kHz, 8000kHz, ...
- Adaptive clocking
J-Link>i
JTAG Id: 0x4F1F0F0F Version: 0x4 Part no: 0xf1f0 Man. Id: 0787
J-Link>testrspeed
Speed test: Reading 8 * 8kb from address 0x00000000 Info: RTCK reaction time is
approx. 126ns
Info: Auto JTAG speed: Adaptive
........
8 kByte read in 82ms ! (99.8 KByte/sec)
J-Link>testrspeed
Speed test: Reading 8 * 128kb from address 0x00000000 ........
128 kByte read in 1197ms ! (109.5 KByte/sec)
C:\temp\openocd-0.5rc1\bin>openocd-0.5.0-rc1.exe -f
interface\jlink.cfg -f target\lpc2468.cfg
(note: this is not proper config, I am testing with an IAR LPC-2468 KS board).
Open On-Chip Debugger 0.5.0-dev (2011-07-11-21:12)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
Warn : Adapter driver 'jlink' did not declare which transports it allows; assumi
ng legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
init_targets
Warning - assuming default core clock 4MHz! Flashing may fail if
actual core clock is different.
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
500 kHz
Info : J-Link initialization started / target CPU reset initiated
Info : J-Link ARM V6 compiled Feb 1 2011 14:28:14
Info : J-Link caps 0x99ff7bbf
Info : J-Link hw version 60000
Info : J-Link hw type J-Link
Info : J-Link max mem block 8864
Info : J-Link configuration
Info : USB-Address: 0xff
Info : Kickstart power on JTAG-pin 19: 0xffffff01
Info : Vref = 3.274 TCK = 1 TDI = 0 TDO = 1 TMS = 0 SRST = 1 TRST = 0
Info : J-Link JTAG Interface ready
Info : clock speed 500 kHz
Info : JTAG tap: lpc2468.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787,
part: 0xf1f0, ver: 0x4)
Info : Embedded ICE version 7
Error: EmbeddedICE v7 handling might be broken
Info : lpc2468.cpu: hardware has 2 breakpoint/watchpoint units
Just wondering who has a nice board file for IAR LPC-2468 KS?
--
Xiaofan
_______________________________________________
Openocd-development mailing list
Openocd-development@lists.berlios.de
https://lists.berlios.de/mailman/listinfo/openocd-development
