This is an automated email from Gerrit.

Andreas Fritiofson (andreas.fritiof...@gmail.com) just uploaded a new patch set 
to Gerrit, which you can find at http://openocd.zylin.com/119

-- gerrit

commit 1c43b43377ed5e0e09a40b09b556b6194dc23958
Author: Andreas Fritiofson <andreas.fritiof...@gmail.com>
Date:   Tue Oct 25 00:47:21 2011 +0200

    armv7a: fix scan-build warnings
    
    "Value stored to 'retval' is never read": Check and propagate error
    "Dereference of null pointer": Probably bogus, maybe triggered by the null
    check on armv7a, so remove the check since it can't be null anyway.
    
    Change-Id: I3bc44e52af1589ff40e6a42deda0ce7f3a25e397
    Signed-off-by: Andreas Fritiofson <andreas.fritiof...@gmail.com>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index d74b99b..67c563e 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -147,6 +147,8 @@ int armv7a_mmu_translate_va(struct target *target,  
uint32_t va, uint32_t *val)
        retval = dpm->instr_read_data_r0(dpm,
                        ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
                        &ttb);
+       if (retval != ERROR_OK)
+               return retval;
        retval = armv7a->armv7a_mmu.read_physical_memory(target,
                        (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
                        4, 1, (uint8_t*)&first_lvl_descriptor);
@@ -461,8 +463,6 @@ static int armv7a_l2x_cache_init(struct target *target, 
uint32_t base, uint32_t
        struct target *curr;
 
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       if (armv7a == NULL)
-               LOG_ERROR("not an armv7a target");
        l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
        l2x_cache->base = base;
        l2x_cache->way = way;
@@ -616,6 +616,7 @@ int armv7a_identify_cache(struct target *target)
                        2, 0,   /* op1, op2 */
                        0, 0,   /* CRn, CRm */
                        &cache_selected);
+       if (retval!=ERROR_OK) goto done;
        /* select instruction cache*/
        /*  MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */
        /*  [0]  : 1 instruction cache selection , 0 data cache selection */

-- 
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