Hallo Jeremy:
Further to my previous e-mails, please find attached a patch to clear R0
on start-up in all or1ksim's test cases under test-code-or1k.
Regards,
Ruben
Index: testsuite/test-code-or1k/cache/cache-asm.S
===================================================================
--- testsuite/test-code-or1k/cache/cache-asm.S (revision 784)
+++ testsuite/test-code-or1k/cache/cache-asm.S (working copy)
@@ -49,6 +49,10 @@
.org 0x100
reset_vector:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
Index: testsuite/test-code-or1k/cfg/cfg.S
===================================================================
--- testsuite/test-code-or1k/cfg/cfg.S (revision 784)
+++ testsuite/test-code-or1k/cfg/cfg.S (working copy)
@@ -30,6 +30,10 @@
.section .except,"ax"
.org 0x100
_reset:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.addi r1,r0,0x7f00
l.movhi r2,hi(_main)
l.ori r2,r2,lo(_main)
Index: testsuite/test-code-or1k/except-test/except-test-s.S
===================================================================
--- testsuite/test-code-or1k/except-test/except-test-s.S (revision 784)
+++ testsuite/test-code-or1k/except-test/except-test-s.S (working copy)
@@ -77,6 +77,11 @@
reset_vector:
l.nop
l.nop
+
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
Index: testsuite/test-code-or1k/except/except.S
===================================================================
--- testsuite/test-code-or1k/except/except.S (revision 784)
+++ testsuite/test-code-or1k/except/except.S (working copy)
@@ -58,6 +58,11 @@
reset_vector:
l.nop
l.nop
+
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
Index: testsuite/test-code-or1k/ext/ext.S
===================================================================
--- testsuite/test-code-or1k/ext/ext.S (revision 784)
+++ testsuite/test-code-or1k/ext/ext.S (working copy)
@@ -121,6 +121,10 @@
.section .text
start_test:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
/* Test l.extbs */
CHECK_HIGH3_CLEAR(l.extbs, 0x7f)
CHECK_HIGH3_CLEAR(l.extbs, 0x53)
Index: testsuite/test-code-or1k/flag/flag.S
===================================================================
--- testsuite/test-code-or1k/flag/flag.S (revision 784)
+++ testsuite/test-code-or1k/flag/flag.S (working copy)
@@ -36,6 +36,11 @@
.org 0x100
_reset:
l.nop
+
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.movhi r10,0x8000
l.addi r11,r0,-1
l.addi r12,r0,2
Index: testsuite/test-code-or1k/fp/fp.S
===================================================================
--- testsuite/test-code-or1k/fp/fp.S (revision 784)
+++ testsuite/test-code-or1k/fp/fp.S (working copy)
@@ -353,6 +353,10 @@
.org 0x100
_reset:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.movhi r1,hi(_stack) /* Set up the stack */
l.ori r1,r1,lo(_stack)
Index: testsuite/test-code-or1k/inst-set-test/inst-set-test.S
===================================================================
--- testsuite/test-code-or1k/inst-set-test/inst-set-test.S (revision 784)
+++ testsuite/test-code-or1k/inst-set-test/inst-set-test.S (working copy)
@@ -72,6 +72,10 @@
.org 0x100
.global _reset
_reset:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.movhi r1,hi(_stack) /* Set up the stack */
l.ori r1,r1,lo(_stack)
Index: testsuite/test-code-or1k/int-test/int-test.S
===================================================================
--- testsuite/test-code-or1k/int-test/int-test.S (revision 784)
+++ testsuite/test-code-or1k/int-test/int-test.S (working copy)
@@ -58,6 +58,10 @@
.org 0x100
_reset_vector:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
Index: testsuite/test-code-or1k/mc-common/except-mc.S
===================================================================
--- testsuite/test-code-or1k/mc-common/except-mc.S (revision 784)
+++ testsuite/test-code-or1k/mc-common/except-mc.S (working copy)
@@ -55,6 +55,11 @@
reset_vector:
l.nop
l.nop
+
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to
zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
Index: testsuite/test-code-or1k/uos/except-or32.S
===================================================================
--- testsuite/test-code-or1k/uos/except-or32.S (revision 784)
+++ testsuite/test-code-or1k/uos/except-or32.S (working copy)
@@ -200,6 +200,10 @@
.org 0x100
reset_vector:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ l.andi r0,r0,0x0
+
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
_______________________________________________
OpenRISC mailing list
[email protected]
http://lists.openrisc.net/listinfo/openrisc
