Hi Gavin

Thanks a ton for your detailed response! I was getting at exactly the issue of 
whether it is possible to have a TLB miss while already servicing a user-level 
miss. 
I'm actually a bit surprised that all the TSB and hash-table are maintained in 
physical memory. I had somehow assumed that due to its size, some portion of it 
would be virtually allocated by the VM system.

I had another question, one which might be rather vague I'm afraid. I have been 
running some experiments with the Simics infrastructure (which models and 
Ultrasparc III Cu running Solaris 10) and have been tracking TLB miss patterns 
for a variety of workloads. Now, when there is a TLB miss, I am seeing that the 
OS gets an interrupt and services the miss, after which it inserts the 
appropriate entry into the TLB. What is puzzling me is that the OS also seems 
to be removing and adding TLB entries in the fully-associative 16-entry DTLB 
without actually experiencing a TLB miss. I am at a loss as to why the OS might 
want to tamper with this TLB without incurring a previous miss...so my question 
is, are there instances when the OS removes and adds TLB entries without and 
initial TLB miss?

Thanks a bunch again!
Abhishek
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