Andy Polyakov wrote: | | [...] | It might happen that RC4_INT=char would perform better on plain P4 as | well... It's never simple, huh?
The fact that RC4_INT=long is slower on Nocona may be explained by the small 16 kB L1 data cache of this processor (to be compared with 64 kB on AMD processors). When RC4_INT=long, the RC4 table occupies 256*8 = 2 kB in memory, this probably forces some data out of L1 cache... But, heh, maybe it's not that simple ! | [...] | All rc4-amd64s rely on partial register arithmetics, something P4 core | was never good at [which is why you see "How IA32E would perform remains | to be seen..." in commentary section]... I thought P4 were pretty good on partial register arithmetic. Hmm, my source was unreliable :) -- Marc Bevand http://epita.fr/~bevand_m Computer Science School EPITA - System, Network and Security Dept. ______________________________________________________________________ OpenSSL Project http://www.openssl.org Development Mailing List [EMAIL PROTECTED] Automated List Manager [EMAIL PROTECTED]
