It's all in the interest of increased processing speed. Tighter models, such as strict ordering, are inherently slower than reordering models. The more reordering that can be done the better performance can be. Write combining buffers are an extreme example where overwriting the same address in memory can result in only the final value actually being written to the memory bus (ie. the initial and intermediate writes to the same address never make it to the bus), however these are usually only used for specific memory-mapped devices such as video frame buffers.
-----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of David C. Partridge Sent: Thursday, 7 April 2005 6:17 PM To: openssl-dev@openssl.org Subject: RE: OpenSSL use of DCLP may not be thread-safe on multiple processors Thanks all. It strikes me that the H/W designers have played a bit "fast and loose" with the cache consistency issue here - I believe I understand the C/C++ optimisation issues, and these CAN be worked around (IMHO) within the rules of the standard by using bool in some cases. However I've notified our dev folks to remove the few cases where we've used this technique as it is certainly dangerous. Dave ______________________________________________________________________ OpenSSL Project http://www.openssl.org Development Mailing List openssl-dev@openssl.org Automated List Manager [EMAIL PROTECTED] ______________________________________________________________________ OpenSSL Project http://www.openssl.org Development Mailing List openssl-dev@openssl.org Automated List Manager [EMAIL PROTECTED]
