As some of you may be aware the new Oracle SPARC T4 processor has
hardware crypto support just like its predecessors SPARC T1,T2,T3.
However unlike the prior SPARC T series processors the hardware crypto
is not hyper-privileged but is instead new instructions accessible from
unprivileged userland code. Basically a very similar model to what is
available in Intel processors with AES-NI, but it is much more than just
AES. The hardware supports instructions for:
AES, DES, Camellia
MD5, SHA1, SHA256, SHA512
MONTMUL, MPUL
We currently have an new "t4" engine implemented that provides support
for AES,MD5,SHA1,SHA256/384/512 using the hardware instructions on the
SPARC T4 processor.
We implemented this as a new engine because at the time we made the
choices this is how Intel AES-NI support was done in OpenSSL CVS head.
We have noticed that the Intel AES-NI support has changed and it is now
directly integrated rather than being an engine.
We would like to contribute patches for SPARC T4 support to OpenSSL with
the intention of them being part of the core release.
We can contribute the engine as we currently have it if that is of
interest. However we would like to know if the OpenSSL community
believes that SPARC T4 should be done similar to Intel AES-NI instead
and integrated "inline" into the main implementation.
--
Darren J Moffat
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