This is the first phase of changes to support the new cryptographic
opcodes found starting in the SPARC-T4 processor.
It first builds the infrastructure for feature presence detection,
then adds support for all of the hashing functions implemented in
current cpus (MD5, SHA1, SHA256, SHA512).
Here are some benchmarks on a SPARC T4-2 with these changes applied.
type 16 bytes 64 bytes 256 bytes 1024 bytes 8192 bytes
md5 14423.71k 50416.70k 173663.49k 445940.05k 816587.27k
sha1 33231.78k 115492.48k 318273.91k 579320.83k 759701.50k
sha256 46641.41k 157805.85k 419859.54k 708643.16k 889514.67k
sha512 50184.57k 202770.99k 529172.57k 1023763.11k 1405414.06k
These numbers, with crypto-opcode-disabled numbers for comparison,
are duplicated in the relevant patch log messages.
I have cipher patches for AES, DES, and CAMELLIA as well but I would
like to refine them a bit before I make a formal submission. And once
I get those changes refined I will work on mongomery multiply,
montgomery square-root, etc. which these chips also support directly.
I've tested these changes on all of {static,shared}/linux{,64}-sparcv9
Oracle provided me with programmer's manuals that document these
instructions, and I've been promised that these would be made public
at some point in the not too distant future. But these instructions
are very straightforward, and when I post the AES changes later on
you will see that the AES instructions are virtually identical to
the AESNI stuff from Intel.
All of the patches are against mainline, but should be backportable
to 1.0.x without much difficulty.
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