Hello community,
here is the log from the commit of package kernel-source for openSUSE:Factory
checked in at 2017-03-10 20:53:40
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/kernel-source (Old)
and /work/SRC/openSUSE:Factory/.kernel-source.new (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "kernel-source"
Fri Mar 10 20:53:40 2017 rev:353 rq:477431 version:4.10.1
Changes:
--------
--- /work/SRC/openSUSE:Factory/kernel-source/dtb-aarch64.changes
2017-02-27 18:56:28.124706129 +0100
+++ /work/SRC/openSUSE:Factory/.kernel-source.new/dtb-aarch64.changes
2017-03-10 20:53:43.333530872 +0100
@@ -1,0 +2,32 @@
+Tue Mar 7 10:29:19 CET 2017 - jdelv...@suse.de
+
+- Revert "drm/amdgpu: update tile table for oland/hainan"
+ (boo#1027378).
+- commit f764d42
+
+-------------------------------------------------------------------
+Mon Mar 6 09:05:39 CET 2017 - mkube...@suse.cz
+
+- bonding: use ETH_MAX_MTU as max mtu (bsc#1027798).
+- commit 2f8350b
+
+-------------------------------------------------------------------
+Thu Mar 2 14:05:23 CET 2017 - mkube...@suse.cz
+
+- Update patches.kernel.org/patch-4.10.1 references (add CVE-2017-6347
bsc#1027179).
+- commit 8c10701
+
+-------------------------------------------------------------------
+Thu Mar 2 14:00:10 CET 2017 - mkube...@suse.cz
+
+- sctp: deny peeloff operation on asocs with threads sleeping
+ on it (CVE-2017-6353 bsc#1027066).
+- commit 8fb16bc
+
+-------------------------------------------------------------------
+Mon Feb 27 12:17:22 CET 2017 - jsl...@suse.cz
+
+- crypto: algif_hash - avoid zero-sized array (bnc#1007962).
+- commit 2f945d3
+
+-------------------------------------------------------------------
@@ -5,0 +38,7 @@
+
+-------------------------------------------------------------------
+Tue Feb 21 10:34:18 CET 2017 - ti...@suse.de
+
+- drm/i915/gvt: Fix superfluous newline in GVT_DISPLAY_READY
+ env var (bsc#1025903).
+- commit cac9478
dtb-armv6l.changes: same change
dtb-armv7l.changes: same change
kernel-64kb.changes: same change
kernel-debug.changes: same change
kernel-default.changes: same change
kernel-docs.changes: same change
kernel-lpae.changes: same change
kernel-obs-build.changes: same change
kernel-obs-qa.changes: same change
kernel-pae.changes: same change
kernel-source.changes: same change
kernel-syms.changes: same change
kernel-syzkaller.changes: same change
kernel-vanilla.changes: same change
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ dtb-aarch64.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:49.756620560 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:49.760619993 +0100
@@ -24,7 +24,7 @@
Name: dtb-aarch64
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
dtb-armv6l.spec: same change
dtb-armv7l.spec: same change
++++++ kernel-64kb.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:49.892601288 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:49.892601288 +0100
@@ -60,7 +60,7 @@
Group: System/Kernel
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
kernel-debug.spec: same change
kernel-default.spec: same change
++++++ kernel-docs.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:49.968590517 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:49.972589951 +0100
@@ -44,7 +44,7 @@
Group: Documentation/Man
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
++++++ kernel-lpae.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:49.996586550 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:50.000585984 +0100
@@ -60,7 +60,7 @@
Group: System/Kernel
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
++++++ kernel-obs-build.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:50.036580881 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:50.040580315 +0100
@@ -59,7 +59,7 @@
Group: SLES
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
kernel-obs-qa.spec: same change
++++++ kernel-pae.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:50.096572379 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:50.096572379 +0100
@@ -60,7 +60,7 @@
Group: System/Kernel
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
++++++ kernel-source.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:50.144565578 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:50.144565578 +0100
@@ -32,7 +32,7 @@
Group: Development/Sources
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
++++++ kernel-syms.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:50.184559910 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:50.188559343 +0100
@@ -27,7 +27,7 @@
Version: 4.10.1
%if %using_buildservice
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
++++++ kernel-syzkaller.spec ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:50.220554808 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:50.224554241 +0100
@@ -60,7 +60,7 @@
Group: System/Kernel
Version: 4.10.1
%if 0%{?is_kotd}
-Release: <RELEASE>.g1ecd5af
+Release: <RELEASE>.gf764d42
%else
Release: 0
%endif
kernel-vanilla.spec: same change
++++++ patches.fixes.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/bonding-use-ETH_MAX_MTU-as-max-mtu.patch
new/patches.fixes/bonding-use-ETH_MAX_MTU-as-max-mtu.patch
--- old/patches.fixes/bonding-use-ETH_MAX_MTU-as-max-mtu.patch 1970-01-01
01:00:00.000000000 +0100
+++ new/patches.fixes/bonding-use-ETH_MAX_MTU-as-max-mtu.patch 2017-03-07
10:29:19.000000000 +0100
@@ -0,0 +1,37 @@
+From: WANG Cong <xiyou.wangc...@gmail.com>
+Date: Thu, 2 Mar 2017 12:24:36 -0800
+Subject: bonding: use ETH_MAX_MTU as max mtu
+Patch-mainline: v4.11-rc1
+Git-commit: 31c05415f5b471fd333fe42629788364faea8e0d
+References: bsc#1027798
+
+This restores the ability of setting bond device's mtu to 9000.
+
+Fixes: 91572088e3fd ("net: use core MTU range checking in core net infra")
+Reported-by: daz...@gmail.com
+Reported-by: Brad Campbell <lists2...@fnarfbargle.com>
+Cc: Jarod Wilson <ja...@redhat.com>
+Signed-off-by: Cong Wang <xiyou.wangc...@gmail.com>
+Signed-off-by: Jay Vosburgh <jay.vosbu...@canonical.com>
+Signed-off-by: David S. Miller <da...@davemloft.net>
+Acked-by: Michal Kubecek <mkube...@suse.cz>
+
+---
+ drivers/net/bonding/bond_main.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
+index 8029dd4912b6..644d2bf0c451 100644
+--- a/drivers/net/bonding/bond_main.c
++++ b/drivers/net/bonding/bond_main.c
+@@ -4185,6 +4185,7 @@ void bond_setup(struct net_device *bond_dev)
+
+ /* Initialize the device entry points */
+ ether_setup(bond_dev);
++ bond_dev->max_mtu = ETH_MAX_MTU;
+ bond_dev->netdev_ops = &bond_netdev_ops;
+ bond_dev->ethtool_ops = &bond_ethtool_ops;
+
+--
+2.12.0
+
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/crypto-algif_hash-avoid-zero-sized-array.patch
new/patches.fixes/crypto-algif_hash-avoid-zero-sized-array.patch
--- old/patches.fixes/crypto-algif_hash-avoid-zero-sized-array.patch
1970-01-01 01:00:00.000000000 +0100
+++ new/patches.fixes/crypto-algif_hash-avoid-zero-sized-array.patch
2017-03-07 10:29:19.000000000 +0100
@@ -0,0 +1,66 @@
+From: Jiri Slaby <jsl...@suse.cz>
+Date: Thu, 15 Dec 2016 14:31:01 +0100
+Subject: crypto: algif_hash - avoid zero-sized array
+Git-commit: 6207119444595d287b1e9e83a2066c17209698f3
+Patch-mainline: 4.11-rc1
+References: bnc#1007962
+
+With this reproducer:
+ struct sockaddr_alg alg = {
+ .salg_family = 0x26,
+ .salg_type = "hash",
+ .salg_feat = 0xf,
+ .salg_mask = 0x5,
+ .salg_name = "digest_null",
+ };
+ int sock, sock2;
+
+ sock = socket(AF_ALG, SOCK_SEQPACKET, 0);
+ bind(sock, (struct sockaddr *)&alg, sizeof(alg));
+ sock2 = accept(sock, NULL, NULL);
+ setsockopt(sock, SOL_ALG, ALG_SET_KEY, "\x9b\xca", 2);
+ accept(sock2, NULL, NULL);
+
+==== 8< ======== 8< ======== 8< ======== 8< ====
+
+one can immediatelly see an UBSAN warning:
+UBSAN: Undefined behaviour in crypto/algif_hash.c:187:7
+variable length array bound value 0 <= 0
+CPU: 0 PID: 15949 Comm: syz-executor Tainted: G E
4.4.30-0-default #1
+...
+Call Trace:
+...
+ [<ffffffff81d598fd>] ? __ubsan_handle_vla_bound_not_positive+0x13d/0x188
+ [<ffffffff81d597c0>] ? __ubsan_handle_out_of_bounds+0x1bc/0x1bc
+ [<ffffffffa0e2204d>] ? hash_accept+0x5bd/0x7d0 [algif_hash]
+ [<ffffffffa0e2293f>] ? hash_accept_nokey+0x3f/0x51 [algif_hash]
+ [<ffffffffa0e206b0>] ? hash_accept_parent_nokey+0x4a0/0x4a0 [algif_hash]
+ [<ffffffff8235c42b>] ? SyS_accept+0x2b/0x40
+
+It is a correct warning, as hash state is propagated to accept as zero,
+but creating a zero-length variable array is not allowed in C.
+
+Fix this as proposed by Herbert -- do "?: 1" on that site. No sizeof or
+similar happens in the code there, so we just allocate one byte even
+though we do not use the array.
+
+Signed-off-by: Jiri Slaby <jsl...@suse.cz>
+Cc: Herbert Xu <herb...@gondor.apana.org.au>
+Cc: "David S. Miller" <da...@davemloft.net> (maintainer:CRYPTO API)
+Reported-by: Sasha Levin <sasha.le...@oracle.com>
+Signed-off-by: Herbert Xu <herb...@gondor.apana.org.au>
+---
+ crypto/algif_hash.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/crypto/algif_hash.c
++++ b/crypto/algif_hash.c
+@@ -245,7 +245,7 @@ static int hash_accept(struct socket *so
+ struct alg_sock *ask = alg_sk(sk);
+ struct hash_ctx *ctx = ask->private;
+ struct ahash_request *req = &ctx->req;
+- char state[crypto_ahash_statesize(crypto_ahash_reqtfm(req))];
++ char state[crypto_ahash_statesize(crypto_ahash_reqtfm(req)) ? : 1];
+ struct sock *sk2;
+ struct alg_sock *ask2;
+ struct hash_ctx *ctx2;
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
---
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
1970-01-01 01:00:00.000000000 +0100
+++
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
2017-03-07 10:29:19.000000000 +0100
@@ -0,0 +1,458 @@
+From: Jean Delvare <jdelv...@suse.de>
+Subject: Revert "drm/amdgpu: update tile table for oland/hainan"
+References: boo#1027378
+Patch-mainline: No, will be fixed differently in v4.11
+
+Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for
+oland/hainan") as it is causing ugly visual artefacts on at least
+Oland. This is only an optimization so we can live without it.
+
+This fixes kernel bug #194761:
+amdgpu driver breaks on Oland (SI)
+https://bugzilla.kernel.org/show_bug.cgi?id=194761
+
+Signed-off-by: Jean Delvare <jdelv...@suse.de>
+Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
+Acked-by: Alex Deucher <alexander.deuc...@amd.com>
+Cc: Flora Cui <flora....@amd.com>
+Cc: Junwei Zhang <jerry.zh...@amd.com>
+---
+Note: This is for stable v4.10 branch only. v4.11 and later have a
+different fix, but it's much larger and more intrusive so not suitable
+for a stable branch.
+
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 330
++++++++++++++--------------------
+ 1 file changed, 139 insertions(+), 191 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+@@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i
+ for (reg_offset = 0; reg_offset < num_tile_mode_states;
reg_offset++) {
+ switch (reg_offset) {
+ case 0:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 1:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 2:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 3:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 4:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 5:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 6:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 7:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 8:
+- gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 9:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 10:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 11:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 12:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 13:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 14:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 15:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 16:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 17:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
+- break;
+- case 18:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2));
+- break;
+- case 19:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
+- break;
+- case 20:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 21:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 22:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 23:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 24:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 25:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 26:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 27:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 28:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 29:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 30:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ NUM_BANKS(ADDR_SURF_8_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ break;
+ default:
+- continue;
++ gb_tile_moden = 0;
++ break;
+ }
+ adev->gfx.config.tile_mode_array[reg_offset] =
gb_tile_moden;
+ WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/drm-i915-gvt-Fix-superfluous-newline-in-GVT_DISPLAY_
new/patches.fixes/drm-i915-gvt-Fix-superfluous-newline-in-GVT_DISPLAY_
--- old/patches.fixes/drm-i915-gvt-Fix-superfluous-newline-in-GVT_DISPLAY_
1970-01-01 01:00:00.000000000 +0100
+++ new/patches.fixes/drm-i915-gvt-Fix-superfluous-newline-in-GVT_DISPLAY_
2017-03-07 10:29:19.000000000 +0100
@@ -0,0 +1,56 @@
+From: Takashi Iwai <ti...@suse.de>
+Date: Mon, 20 Feb 2017 14:43:35 +0100
+Subject: [PATCH] drm/i915/gvt: Fix superfluous newline in GVT_DISPLAY_READY
+ env var
+Date: Mon, 20 Feb 2017 14:58:25 +0100
+Message-Id: <20170220135825.11430-1-ti...@suse.de>
+References: bsc#1025903
+Patch-mainline: Submitted, intel-gfx ML
+
+send_display_send_uevent() sends two environment variable, and the
+first one GVT_DISPLAY_READY is set including a new line at the end of
+the string; that is obviously superfluous and wrong -- at least, it
+*looks* so when you only read the code.
+
+However, it doesn't appear in the actual output by a (supposedly
+unexpected) trick. The code uses snprintf() and truncates the string
+in size 20 bytes. This makes the string as GVT_DISPLAY_READY=0 or
+...=1 including the trailing NUL-letter. That is, the '\n' found in
+the format string is always cut off as a result.
+
+Although the code gives the correct result, it is confusing. This
+patch addresses it, just removing the superfluous '\n' from the format
+string for avoiding further confusion. If the argument "ready" were
+not a bool, the size 20 should be corrected as well. But it's a
+bool, so we can leave the magic number 20 as is for now.
+
+FWIW, the bug was spotted by a new GCC7 warning:
+ drivers/gpu/drm/i915/gvt/handlers.c: In function 'pvinfo_mmio_write':
+ drivers/gpu/drm/i915/gvt/handlers.c:1042:34: error: 'snprintf' output
truncated before the last format character [-Werror=format-truncation=]
+ snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready);
+ ^~~~~~~~~~~~~~~~~~~~~~~~
+ drivers/gpu/drm/i915/gvt/handlers.c:1042:2: note: 'snprintf' output 21 bytes
into a destination of size 20
+ snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready);
+ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Fixes: 04d348ae3f0a ("drm/i915/gvt: vGPU display virtualization")
+Bugzilla: https://bugzilla.suse.com/show_bug.cgi?id=1025903
+Reported-by: Richard Biener <rguent...@suse.com>
+Cc: <sta...@vger.kernel.org>
+Signed-off-by: Takashi Iwai <ti...@suse.de>
+
+---
+ drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/gvt/handlers.c
++++ b/drivers/gpu/drm/i915/gvt/handlers.c
+@@ -1039,7 +1039,7 @@ static int send_display_ready_uevent(str
+ char vmid_str[20];
+ char display_ready_str[20];
+
+- snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready);
++ snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
+ env[0] = display_ready_str;
+
+ snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/sctp-deny-peeloff-operation-on-asocs-with-threads-sl.patch
new/patches.fixes/sctp-deny-peeloff-operation-on-asocs-with-threads-sl.patch
---
old/patches.fixes/sctp-deny-peeloff-operation-on-asocs-with-threads-sl.patch
1970-01-01 01:00:00.000000000 +0100
+++
new/patches.fixes/sctp-deny-peeloff-operation-on-asocs-with-threads-sl.patch
2017-03-07 10:29:19.000000000 +0100
@@ -0,0 +1,69 @@
+From: Marcelo Ricardo Leitner <marcelo.leit...@gmail.com>
+Date: Thu, 23 Feb 2017 09:31:18 -0300
+Subject: sctp: deny peeloff operation on asocs with threads sleeping on it
+Patch-mainline: v4.11-rc1
+Git-commit: dfcb9f4f99f1e9a49e43398a7bfbf56927544af1
+References: CVE-2017-6353 bsc#1027066
+
+commit 2dcab5984841 ("sctp: avoid BUG_ON on sctp_wait_for_sndbuf")
+attempted to avoid a BUG_ON call when the association being used for a
+sendmsg() is blocked waiting for more sndbuf and another thread did a
+peeloff operation on such asoc, moving it to another socket.
+
+As Ben Hutchings noticed, then in such case it would return without
+locking back the socket and would cause two unlocks in a row.
+
+Further analysis also revealed that it could allow a double free if the
+application managed to peeloff the asoc that is created during the
+sendmsg call, because then sctp_sendmsg() would try to free the asoc
+that was created only for that call.
+
+This patch takes another approach. It will deny the peeloff operation
+if there is a thread sleeping on the asoc, so this situation doesn't
+exist anymore. This avoids the issues described above and also honors
+the syscalls that are already being handled (it can be multiple sendmsg
+calls).
+
+Joint work with Xin Long.
+
+Fixes: 2dcab5984841 ("sctp: avoid BUG_ON on sctp_wait_for_sndbuf")
+Cc: Alexander Popov <alex.po...@linux.com>
+Cc: Ben Hutchings <b...@decadent.org.uk>
+Signed-off-by: Marcelo Ricardo Leitner <marcelo.leit...@gmail.com>
+Signed-off-by: Xin Long <lucien....@gmail.com>
+Signed-off-by: David S. Miller <da...@davemloft.net>
+Acked-by: Michal Kubecek <mkube...@suse.cz>
+
+---
+ net/sctp/socket.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/net/sctp/socket.c b/net/sctp/socket.c
+index 1b5d669e3029..d04a8b66098c 100644
+--- a/net/sctp/socket.c
++++ b/net/sctp/socket.c
+@@ -4734,6 +4734,12 @@ int sctp_do_peeloff(struct sock *sk, sctp_assoc_t id,
struct socket **sockp)
+ if (!asoc)
+ return -EINVAL;
+
++ /* If there is a thread waiting on more sndbuf space for
++ * sending on this asoc, it cannot be peeled.
++ */
++ if (waitqueue_active(&asoc->wait))
++ return -EBUSY;
++
+ /* An association cannot be branched off from an already peeled-off
+ * socket, nor is this supported for tcp style sockets.
+ */
+@@ -7426,8 +7432,6 @@ static int sctp_wait_for_sndbuf(struct sctp_association
*asoc, long *timeo_p,
+ */
+ release_sock(sk);
+ current_timeo = schedule_timeout(current_timeo);
+- if (sk != asoc->base.sk)
+- goto do_error;
+ lock_sock(sk);
+
+ *timeo_p = current_timeo;
+--
+2.11.1
+
++++++ patches.kernel.org.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore' old/patches.kernel.org/patch-4.10.1
new/patches.kernel.org/patch-4.10.1
--- old/patches.kernel.org/patch-4.10.1 2017-02-26 13:43:10.000000000 +0100
+++ new/patches.kernel.org/patch-4.10.1 2017-03-02 14:05:23.000000000 +0100
@@ -1,6 +1,6 @@
From: Jiri Slaby <jsl...@suse.cz>
Subject: Linux 4.10.1
-References: bnc#1012628
+References: CVE-2017-6347 bnc#1012628 bsc#1027179
Patch-mainline: 4.10.1
Git-commit: fa7f138ac4c70dc00519c124cf7cd4862a0a5b0e
Git-commit: 575ddce0507789bf9830d089557d2199d2f91865
++++++ series.conf ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:51.212414237 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:51.216413670 +0100
@@ -179,6 +179,7 @@
########################################################
patches.suse/connector-read-mostly
patches.suse/kbd-ignore-gfx.patch
+ patches.fixes/crypto-algif_hash-avoid-zero-sized-array.patch
########################################################
#
@@ -208,6 +209,8 @@
########################################################
# Networking, IPv6
########################################################
+ patches.fixes/sctp-deny-peeloff-operation-on-asocs-with-threads-sl.patch
+ patches.fixes/bonding-use-ETH_MAX_MTU-as-max-mtu.patch
########################################################
# Netfilter
@@ -315,6 +318,8 @@
########################################################
patches.fixes/drm-i915-Fix-S4-resume-breakage
patches.drivers/drm-reference-count-event-completion
+ patches.fixes/drm-i915-gvt-Fix-superfluous-newline-in-GVT_DISPLAY_
+ patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
########################################################
# video4linux
++++++ source-timestamp ++++++
--- /var/tmp/diff_new_pack.cBbsOD/_old 2017-03-10 20:53:51.252408569 +0100
+++ /var/tmp/diff_new_pack.cBbsOD/_new 2017-03-10 20:53:51.252408569 +0100
@@ -1,3 +1,3 @@
-2017-02-26 13:43:10 +0100
-GIT Revision: 1ecd5afe5e60593ba814ba88b0728a4efae7724c
+2017-03-07 10:29:19 +0100
+GIT Revision: f764d4216e0a84a6577e402acf62abc0ca18f0dc
GIT Branch: stable
