Hello community,
here is the log from the commit of package kernel-source for openSUSE:Factory
checked in at 2017-05-24 16:46:08
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Comparing /work/SRC/openSUSE:Factory/kernel-source (Old)
and /work/SRC/openSUSE:Factory/.kernel-source.new (New)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "kernel-source"
Wed May 24 16:46:08 2017 rev:365 rq:496991 version:4.11.2
Changes:
--------
--- /work/SRC/openSUSE:Factory/kernel-source/dtb-aarch64.changes
2017-05-18 20:36:24.296151936 +0200
+++ /work/SRC/openSUSE:Factory/.kernel-source.new/dtb-aarch64.changes
2017-05-24 16:46:10.290004909 +0200
@@ -1,0 +2,13 @@
+Sat May 20 20:13:12 CEST 2017 - jsl...@suse.cz
+
+- Linux 4.11.2 (bnc#1012628).
+- commit 03903d8
+
+-------------------------------------------------------------------
+Fri May 19 12:36:38 CEST 2017 - jdelv...@suse.de
+
+- Revert "drm/amdgpu: update tile table for oland/hainan"
+ (boo#1027378, boo#1039806).
+- commit 2e66df6
+
+-------------------------------------------------------------------
dtb-armv6l.changes: same change
dtb-armv7l.changes: same change
kernel-64kb.changes: same change
kernel-debug.changes: same change
kernel-default.changes: same change
kernel-docs.changes: same change
kernel-lpae.changes: same change
kernel-obs-build.changes: same change
kernel-obs-qa.changes: same change
kernel-pae.changes: same change
kernel-source.changes: same change
kernel-syms.changes: same change
kernel-syzkaller.changes: same change
kernel-vanilla.changes: same change
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Other differences:
------------------
++++++ dtb-aarch64.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:15.961206462 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:15.961206462 +0200
@@ -17,7 +17,7 @@
%define srcversion 4.11
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%include %_sourcedir/kernel-spec-macros
@@ -29,9 +29,9 @@
%(chmod +x
%_sourcedir/{guards,apply-patches,check-for-config-changes,group-source-files.pl,find-provides,find-requires,split-modules,modversions,kabi.pl,mkspec,compute-PATCHVERSION.sh,arch-symbols,log.sh,try-disable-staging-driver,compress-vmlinux.sh,mkspec-dtb})
Name: dtb-aarch64
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
dtb-armv6l.spec: same change
dtb-armv7l.spec: same change
++++++ kernel-64kb.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.053193511 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.057192948 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.11
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel with 64kb PAGE_SIZE
License: GPL-2.0
Group: System/Kernel
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
kernel-debug.spec: same change
kernel-default.spec: same change
++++++ kernel-docs.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.149179997 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.153179434 +0200
@@ -16,7 +16,7 @@
#
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%include %_sourcedir/kernel-spec-macros
@@ -42,9 +42,9 @@
Summary: Kernel Documentation (man pages)
License: GPL-2.0
Group: Documentation/Man
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
++++++ kernel-lpae.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.173176619 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.177176056 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.11
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel for LPAE enabled systems
License: GPL-2.0
Group: System/Kernel
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
++++++ kernel-obs-build.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.201172677 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.209171551 +0200
@@ -19,7 +19,7 @@
#!BuildIgnore: post-build-checks
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%define vanilla_only 0
@@ -57,9 +57,9 @@
Summary: package kernel and initrd for OBS VM builds
License: GPL-2.0
Group: SLES
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
++++++ kernel-obs-qa.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.241167047 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.241167047 +0200
@@ -17,7 +17,7 @@
# needsrootforbuild
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%include %_sourcedir/kernel-spec-macros
@@ -36,9 +36,9 @@
Summary: Basic QA tests for the kernel
License: GPL-2.0
Group: SLES
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
++++++ kernel-pae.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.269163104 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.273162542 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.11
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel with PAE Support
License: GPL-2.0
Group: System/Kernel
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
++++++ kernel-source.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.305158037 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.305158037 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.11
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%define vanilla_only 0
@@ -30,9 +30,9 @@
Summary: The Linux Kernel Sources
License: GPL-2.0
Group: Development/Sources
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
++++++ kernel-syms.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.333154095 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.337153532 +0200
@@ -24,10 +24,10 @@
Summary: Kernel Symbol Versions (modversions)
License: GPL-2.0
Group: Development/Sources
-Version: 4.11.1
+Version: 4.11.2
%if %using_buildservice
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
++++++ kernel-syzkaller.spec ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:16.361150154 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:16.365149591 +0200
@@ -18,7 +18,7 @@
%define srcversion 4.11
-%define patchversion 4.11.1
+%define patchversion 4.11.2
%define variant %{nil}
%define vanilla_only 0
@@ -58,9 +58,9 @@
Summary: Kernel used for fuzzing by syzkaller
License: GPL-2.0
Group: System/Kernel
-Version: 4.11.1
+Version: 4.11.2
%if 0%{?is_kotd}
-Release: <RELEASE>.ga37d575
+Release: <RELEASE>.g03903d8
%else
Release: 0
%endif
kernel-vanilla.spec: same change
++++++ patches.fixes.tar.bz2 ++++++
diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn'
'--exclude=.svnignore'
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
---
old/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
1970-01-01 01:00:00.000000000 +0100
+++
new/patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
2017-05-19 12:36:38.000000000 +0200
@@ -0,0 +1,454 @@
+From: Jean Delvare <jdelv...@suse.de>
+Subject: Revert "drm/amdgpu: update tile table for oland/hainan"
+References: boo#1027378, boo#1039806
+Patch-mainline: Not yet, will send later today
+
+Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for
+oland/hainan") as it is causing ugly visual artefacts on at least
+Oland. This is only an optimization so we can live without it.
+
+This fixes kernel bug #194761:
+amdgpu driver breaks on Oland (SI)
+https://bugzilla.kernel.org/show_bug.cgi?id=194761
+
+Signed-off-by: Jean Delvare <jdelv...@suse.de>
+Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
+Acked-by: Alex Deucher <alexander.deuc...@amd.com>
+Cc: Flora Cui <flora....@amd.com>
+Cc: Junwei Zhang <jerry.zh...@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 330
++++++++++++++--------------------
+ 1 file changed, 139 insertions(+), 191 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+@@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i
+ for (reg_offset = 0; reg_offset < num_tile_mode_states;
reg_offset++) {
+ switch (reg_offset) {
+ case 0:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 1:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 2:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 3:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 4:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 5:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 6:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 7:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 8:
+- gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 9:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 10:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 11:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 12:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 13:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2));
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 14:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 15:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 16:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 17:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
+- break;
+- case 18:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2));
+- break;
+- case 19:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++ PIPE_CONFIG(ADDR_SURF_P4_8x16)
|
++
TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
+- break;
+- case 20:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+- NUM_BANKS(ADDR_SURF_16_BANK) |
+-
TILE_SPLIT(split_equal_to_row_size));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 21:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 22:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++ NUM_BANKS(ADDR_SURF_16_BANK) |
++
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
++
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ break;
+ case 23:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 24:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
++ NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_8_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ break;
+ case 25:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
++ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
++
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
++
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 26:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 27:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 28:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 29:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
+- break;
+- case 30:
+- gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+- PIPE_CONFIG(ADDR_SURF_P2) |
+-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
++ NUM_BANKS(ADDR_SURF_8_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+- NUM_BANKS(ADDR_SURF_4_BANK));
++
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ break;
+ default:
+- continue;
++ gb_tile_moden = 0;
++ break;
+ }
+ adev->gfx.config.tile_mode_array[reg_offset] =
gb_tile_moden;
+ WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
++++++ patches.kernel.org.tar.bz2 ++++++
++++ 5349 lines of diff (skipped)
++++++ series.conf ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:17.409002626 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:17.413002063 +0200
@@ -28,6 +28,7 @@
# Send separate patches upstream if you find a problem...
########################################################
patches.kernel.org/patch-4.11.1
+ patches.kernel.org/patch-4.11.1-2
########################################################
# Build fixes that apply to the vanilla kernel too.
@@ -320,6 +321,7 @@
# DRM/Video
########################################################
patches.fixes/drm-i915-Fix-S4-resume-breakage
+ patches.fixes/drm-amdgpu-revert-update-tile-table-for-oland-hainan.patch
########################################################
# video4linux
++++++ source-timestamp ++++++
--- /var/tmp/diff_new_pack.hzSlJJ/_old 2017-05-24 16:46:17.456995869 +0200
+++ /var/tmp/diff_new_pack.hzSlJJ/_new 2017-05-24 16:46:17.456995869 +0200
@@ -1,3 +1,3 @@
-2017-05-15 16:33:13 +0200
-GIT Revision: a37d5751c526041a9bb99edb9e14baac50cebe67
+2017-05-20 20:13:12 +0200
+GIT Revision: 03903d821e2bb9e4b3e4f22ed40fa0aa04789206
GIT Branch: stable
