Hello community, here is the log from the commit of package xf86-video-ast for openSUSE:Factory checked in at 2015-09-27 08:39:56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/xf86-video-ast (Old) and /work/SRC/openSUSE:Factory/.xf86-video-ast.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "xf86-video-ast" Changes: -------- --- /work/SRC/openSUSE:Factory/xf86-video-ast/xf86-video-ast.changes 2014-09-03 21:19:53.000000000 +0200 +++ /work/SRC/openSUSE:Factory/.xf86-video-ast.new/xf86-video-ast.changes 2015-09-27 08:39:19.000000000 +0200 @@ -1,0 +2,10 @@ +Mon Sep 14 20:30:27 UTC 2015 - zai...@opensuse.org + +- Update to version 1.1.5: + + Support AST2500. + + Fixed Failed to Init when ASPEED Graphics is Secondary. + + Fixed Transient Noise While System Resume from Hibernate. + + Use same search mode criteria with ast drm driver. + + Use proper type. + +------------------------------------------------------------------- Old: ---- xf86-video-ast-1.0.1.tar.bz2 New: ---- xf86-video-ast-1.1.5.tar.bz2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ xf86-video-ast.spec ++++++ --- /var/tmp/diff_new_pack.YiFTNr/_old 2015-09-27 08:39:19.000000000 +0200 +++ /var/tmp/diff_new_pack.YiFTNr/_new 2015-09-27 08:39:19.000000000 +0200 @@ -1,7 +1,7 @@ # # spec file for package xf86-video-ast # -# Copyright (c) 2014 SUSE LINUX Products GmbH, Nuernberg, Germany. +# Copyright (c) 2015 SUSE LINUX GmbH, Nuernberg, Germany. # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,7 +17,7 @@ Name: xf86-video-ast -Version: 1.0.1 +Version: 1.1.5 Release: 0 Summary: ASpeed Technologies video driver for the Xorg X server License: MIT ++++++ xf86-video-ast-1.0.1.tar.bz2 -> xf86-video-ast-1.1.5.tar.bz2 ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/ChangeLog new/xf86-video-ast-1.1.5/ChangeLog --- old/xf86-video-ast-1.0.1/ChangeLog 2014-08-11 05:46:39.000000000 +0200 +++ new/xf86-video-ast-1.1.5/ChangeLog 2015-08-19 03:36:24.000000000 +0200 @@ -1,3 +1,44 @@ +commit 39e80895acb4b818ecc15af51a68178562ebb41d +Author: Y.C. Chen <yc_c...@aspeedtech.com> +Date: Wed Aug 19 09:21:05 2015 +0800 + + Bump Version to 1.1.5 + +commit 74281c4ce201ff04a6672c703d09ed28286f1801 +Author: Y.C. Chen <yc_c...@aspeedtech.com> +Date: Fri Aug 14 15:30:00 2015 +0800 + + Support AST2500 + +commit 9918d6f69ac51d9d27b074e3e490783acda68dca +Author: Y.C. Chen <yc_c...@aspeedtech.com> +Date: Fri Aug 14 10:11:23 2015 +0800 + + Fixed Failed to Init when ASPEED Graphics is Secondary + +commit e545ab905ea120014558d6f1733d87ffde5d5d71 +Author: Y.C. Chen <yc_c...@aspeedtech.com> +Date: Thu Aug 13 15:54:15 2015 +0800 + + Fixed Transient Noise While System Resume from Hibernate + +commit 77e7ac37c6031551f7ad355dc94c4176df4956aa +Author: Y.C. Chen <yc_c...@aspeedtech.com> +Date: Thu Aug 13 15:21:57 2015 +0800 + + use same search mode criteria with ast drm driver + +commit 4f404aa29eea5707cfdfe3dc2c762bd46063dfec +Author: Thomas Klausner <w...@netbsd.org> +Date: Mon Aug 18 05:35:48 2014 +0800 + + Use proper type. + + Two other places in this file already use uint32_t when passing + it to PCI_READ_LONG. + + Signed-off-by: Thomas Klausner <w...@netbsd.org> + commit d531cac475980908ea52309846221a974b8e7efd Author: Y.C. Chen <yc_c...@aspeedtech.com> Date: Fri Aug 8 16:51:07 2014 +0800 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/configure new/xf86-video-ast-1.1.5/configure --- old/xf86-video-ast-1.0.1/configure 2014-08-08 11:01:06.000000000 +0200 +++ new/xf86-video-ast-1.1.5/configure 2015-08-19 03:26:42.000000000 +0200 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.69 for xf86-video-ast 1.0.1. +# Generated by GNU Autoconf 2.69 for xf86-video-ast 1.1.5. # # Report bugs to <https://bugs.freedesktop.org/enter_bug.cgi?product=xorg>. # @@ -591,8 +591,8 @@ # Identity of this package. PACKAGE_NAME='xf86-video-ast' PACKAGE_TARNAME='xf86-video-ast' -PACKAGE_VERSION='1.0.1' -PACKAGE_STRING='xf86-video-ast 1.0.1' +PACKAGE_VERSION='1.1.5' +PACKAGE_STRING='xf86-video-ast 1.1.5' PACKAGE_BUGREPORT='https://bugs.freedesktop.org/enter_bug.cgi?product=xorg' PACKAGE_URL='' @@ -1358,7 +1358,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures xf86-video-ast 1.0.1 to adapt to many kinds of systems. +\`configure' configures xf86-video-ast 1.1.5 to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1428,7 +1428,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of xf86-video-ast 1.0.1:";; + short | recursive ) echo "Configuration of xf86-video-ast 1.1.5:";; esac cat <<\_ACEOF @@ -1558,7 +1558,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -xf86-video-ast configure 1.0.1 +xf86-video-ast configure 1.1.5 generated by GNU Autoconf 2.69 Copyright (C) 2012 Free Software Foundation, Inc. @@ -1973,7 +1973,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by xf86-video-ast $as_me 1.0.1, which was +It was created by xf86-video-ast $as_me 1.1.5, which was generated by GNU Autoconf 2.69. Invocation command line was $ $0 $@ @@ -2841,7 +2841,7 @@ # Define the identity of the package. PACKAGE='xf86-video-ast' - VERSION='1.0.1' + VERSION='1.1.5' cat >>confdefs.h <<_ACEOF @@ -18824,7 +18824,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by xf86-video-ast $as_me 1.0.1, which was +This file was extended by xf86-video-ast $as_me 1.1.5, which was generated by GNU Autoconf 2.69. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -18890,7 +18890,7 @@ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" ac_cs_version="\\ -xf86-video-ast config.status 1.0.1 +xf86-video-ast config.status 1.1.5 configured by $0, generated by GNU Autoconf 2.69, with options \\"\$ac_cs_config\\" diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/configure.ac new/xf86-video-ast-1.1.5/configure.ac --- old/xf86-video-ast-1.0.1/configure.ac 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/configure.ac 2015-08-19 03:24:48.000000000 +0200 @@ -23,7 +23,7 @@ # Initialize Autoconf AC_PREREQ([2.60]) AC_INIT([xf86-video-ast], - [1.0.1], + [1.1.5], [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg], [xf86-video-ast]) AC_CONFIG_SRCDIR([Makefile.am]) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/src/ast.h new/xf86-video-ast-1.1.5/src/ast.h --- old/xf86-video-ast-1.0.1/src/ast.h 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/src/ast.h 2015-08-19 03:24:48.000000000 +0200 @@ -72,6 +72,7 @@ AST2150, AST2300, AST2400, + AST2500, AST1180 } CHIP_ID; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/src/ast_2dtool.c new/xf86-video-ast-1.1.5/src/ast_2dtool.c --- old/xf86-video-ast-1.0.1/src/ast_2dtool.c 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/src/ast_2dtool.c 2015-08-19 03:24:48.000000000 +0200 @@ -241,7 +241,7 @@ ULONG ulData; PFN_bENABLE_CMDQ pfnEnableCMDQ = bEnableCMDQ; - if ( (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) ) + if ( (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500) ) pfnEnableCMDQ = bEnableCMDQ2300; switch (pAST->jChipType) @@ -252,6 +252,7 @@ case AST2150: case AST2300: case AST2400: + case AST2500: *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000; *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/src/ast_accel.c new/xf86-video-ast-1.1.5/src/ast_accel.c --- old/xf86-video-ast-1.0.1/src/ast_accel.c 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/src/ast_accel.c 2015-08-19 03:24:48.000000000 +0200 @@ -191,7 +191,7 @@ /* Solid Lines */ if (pAST->ENGCaps & ENG_CAP_SolidLine) { - if ( (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST1180) ) + if ( (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500) || (pAST->jChipType == AST1180) ) { infoPtr->SubsequentSolidTwoPointLine = AIPSubsequentSolidTwoPointLine; } @@ -208,7 +208,7 @@ /* Dashed Lines */ if (pAST->ENGCaps & ENG_CAP_DashedLine) { - if ( (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST1180) ) + if ( (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500) || (pAST->jChipType == AST1180) ) { infoPtr->SubsequentDashedTwoPointLine = AIPSubsequentDashedTwoPointLine; } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/src/ast_driver.c new/xf86-video-ast-1.1.5/src/ast_driver.c --- old/xf86-video-ast-1.0.1/src/ast_driver.c 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/src/ast_driver.c 2015-08-19 03:24:48.000000000 +0200 @@ -623,17 +623,10 @@ /* Enable VGA MMIO Access */ vASTEnableVGAMMIO(pScrn); - /* Init VGA Adapter */ - if (!xf86IsPrimaryPci(pAST->PciInfo)) - { - ASTInitVGA(pScrn, 0); - } - - vASTOpenKey(pScrn); - bASTRegInit(pScrn); - /* Get Chip Type */ - if (PCI_DEV_REVISION(pAST->PciInfo) >= 0x30) + if (PCI_DEV_REVISION(pAST->PciInfo) >= 0x40) + pAST->jChipType = AST2500; + else if (PCI_DEV_REVISION(pAST->PciInfo) >= 0x30) pAST->jChipType = AST2400; else if (PCI_DEV_REVISION(pAST->PciInfo) >= 0x20) pAST->jChipType = AST2300; @@ -642,6 +635,15 @@ else pAST->jChipType = AST2000; + /* Init VGA Adapter */ + if (!xf86IsPrimaryPci(pAST->PciInfo)) + { + ASTInitVGA(pScrn, 0); + } + + vASTOpenKey(pScrn); + bASTRegInit(pScrn); + /* Get Options from Scratch */ ASTGetScratchOptions(pScrn); @@ -685,7 +687,7 @@ clockRanges->doubleScanAllowed = FALSE; /* Add for AST2100, ycchen@061807 */ - if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST1180)) + if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500) || (pAST->jChipType == AST1180)) { maxPitch = 1920; maxHeight = 1200; @@ -1001,7 +1003,7 @@ xf86DPMSInit(pScreen, ASTDisplayPowerManagementSet, 0); #ifdef AstVideo - if ( (pAST->jChipType == AST1180) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) ) + if ( (pAST->jChipType == AST1180) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500) ) { xf86DrvMsg(pScrn->scrnIndex, X_INFO,"AST Initial Video()\n"); ASTInitVideo(pScreen); @@ -1195,7 +1197,7 @@ if ( (mode->CrtcHDisplay == 1600) && (mode->CrtcVDisplay == 900) ) return MODE_OK; - if ( (pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST1180) ) + if ( (pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500) || (pAST->jChipType == AST1180) ) { if ( (mode->CrtcHDisplay == 1920) && (mode->CrtcVDisplay == 1080) ) return MODE_OK; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/src/ast_mode.c new/xf86-video-ast-1.1.5/src/ast_mode.c --- old/xf86-video-ast-1.0.1/src/ast_mode.c 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/src/ast_mode.c 2015-08-19 03:24:48.000000000 +0200 @@ -197,53 +197,53 @@ }; static VBIOS_ENHTABLE_STRUCT Res1600x900Table[] = { + {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 0x3A }, {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* end */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, + {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* end */ + (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x3A }, }; static VBIOS_ENHTABLE_STRUCT Res1920x1080Table[] = { {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* HDTV 60Hz */ - (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 1, 0x38 }, {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* end */ - (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, + (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 0xFF, 1, 0x38 }, }; /* 16:10 */ static VBIOS_ENHTABLE_STRUCT Res1280x800Table[] = { + {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 35 }, {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, - {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 35 }, - {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 35 }, + {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* end */ + (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x35 }, }; static VBIOS_ENHTABLE_STRUCT Res1440x900Table[] = { + {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 0x36 }, {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, - {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, - {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, + {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* end */ + (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x36 }, }; static VBIOS_ENHTABLE_STRUCT Res1680x1050Table[] = { + {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 2, 0x37 }, {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, - {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, - {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz CVT RB */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, + {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* end */ + (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x37 }, }; static VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = { - {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ - (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, - {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ + {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz CVT RB */ + (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo | AST2500PreCatchCRT), 60, 1, 0x34 }, + {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* end */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, }; @@ -307,6 +307,66 @@ {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ }; +static VBIOS_DCLK_INFO DCLKTable_AST2500 [] = { + {0x40, 0x38, 0x73}, /* 00: VCLK25_175 */ + {0x3A, 0x38, 0x43}, /* 01: VCLK28_322 */ + {0x3E, 0x70, 0x73}, /* 02: VCLK31_5 */ + {0x35, 0x70, 0x43}, /* 03: VCLK36 */ + {0x31, 0x28, 0x73}, /* 04: VCLK40 */ + {0x41, 0x68, 0x73}, /* 05: VCLK49_5 */ + {0x31, 0x68, 0x53}, /* 06: VCLK50 */ + {0x4A, 0x68, 0x73}, /* 07: VCLK56_25 */ + {0x40, 0x68, 0x53}, /* 08: VCLK65 */ + {0x31, 0x60, 0x73}, /* 09: VCLK75 */ + {0x3A, 0x28, 0x43}, /* 0A: VCLK78_75 */ + {0x3E, 0x60, 0x73}, /* 0B: VCLK94_5 */ + {0x35, 0x60, 0x63}, /* 0C: VCLK108 */ + {0x3D, 0x40, 0x63}, /* 0D: VCLK135 */ + {0x4E, 0x60, 0x63}, /* 0E: VCLK157_5 */ + {0x35, 0x60, 0x53}, /* 0F: VCLK162 */ + {0x4C, 0x60, 0x63}, /* 10: VCLK154 */ + {0x4F, 0x48, 0x53}, /* 11: VCLK83.5 */ + {0x46, 0x60, 0x73}, /* 12: VCLK106.5 */ + {0x3C, 0x20, 0x63}, /* 13: VCLK146.25 */ + {0x3D, 0x20, 0x63}, /* 14: VCLK148.5 */ + {0x46, 0x68, 0x53}, /* 15: VCLK71 */ + {0x49, 0x68, 0x43}, /* 16: VCLK88.75 */ + {0x4e, 0x60, 0x73}, /* 17: VCLK119 */ + {0x38, 0x60, 0x73}, /* 18: VCLK85_5 */ + {0x38, 0x20, 0x73}, /* 19: VCLK97_75 */ + {0x4e, 0x60, 0x73}, /* 1A: VCLK118_25 */ +}; + +static VBIOS_DCLK_INFO DCLKTable_AST2500A1 [] = { + {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ + {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ + {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ + {0x76, 0x63, 0x01}, /* 03: VCLK36 */ + {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ + {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ + {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ + {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ + {0x80, 0x64, 0x00}, /* 08: VCLK65 */ + {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ + {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ + {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ + {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ + {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ + {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ + {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ + {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ + {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ + {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ + {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ + {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ + {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ + {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ + {0x58, 0x01, 0x42}, /* 17: VCLK119 */ + {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ + {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ + {0x44, 0x20, 0x43}, /* 1A: VCLK118_25 */ +}; + static VBIOS_DAC_INFO DAC_TEXT[] = { { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, @@ -465,6 +525,9 @@ vSetSyncReg(pScrn, mode, &vgamodeinfo); bSetDACReg(pScrn, mode, &vgamodeinfo); + /* clear video buffer to avoid display noise */ + memset(pAST->FBVirtualAddr, 0x00, pAST->VideoModeInfo.ScreenPitch*pAST->VideoModeInfo.ScreenHeight); + vAST1000DisplayOn(pScrn); } @@ -495,6 +558,8 @@ ASTRecPtr pAST; ULONG ulModeID, ulColorIndex, ulRefreshRate, ulRefreshRateIndex = 0; ULONG ulHBorder, ulVBorder; + Bool check_sync; + PVBIOS_ENHTABLE_STRUCT loop, best = NULL; pAST = ASTPTR(pScrn); @@ -560,27 +625,34 @@ } /* Get Proper Mode Index */ - if (pVGAModeInfo->pEnhTableEntry->Flags & WideScreenMode) - { - /* parsing for wide screen reduced blank mode */ - if ((mode->Flags & V_NVSYNC) && (mode->Flags & V_PHSYNC)) /* CVT RB */ - pVGAModeInfo->pEnhTableEntry++; - } - else - { - ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal); - - while (pVGAModeInfo->pEnhTableEntry->ulRefreshRate < ulRefreshRate) - { - pVGAModeInfo->pEnhTableEntry++; - if ((pVGAModeInfo->pEnhTableEntry->ulRefreshRate > ulRefreshRate) || - (pVGAModeInfo->pEnhTableEntry->ulRefreshRate == 0xFF)) - { - pVGAModeInfo->pEnhTableEntry--; - break; - } - } - } + ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal) + 1; + loop = pVGAModeInfo->pEnhTableEntry; + check_sync = loop->Flags & WideScreenMode; + do { + while (loop->ulRefreshRate != 0xff) { + if ((check_sync) && + (((mode->Flags & V_NVSYNC) && + (loop->Flags & PVSync)) || + ((mode->Flags & V_PVSYNC) && + (loop->Flags & NVSync)) || + ((mode->Flags & V_NHSYNC) && + (loop->Flags & PHSync)) || + ((mode->Flags & V_PHSYNC) && + (loop->Flags & NHSync)))) { + loop++; + continue; + } + if (loop->ulRefreshRate <= ulRefreshRate + && (!best || loop->ulRefreshRate > best->ulRefreshRate)) + best = loop; + loop++; + } + if (best || !check_sync) + break; + check_sync = 0; + } while (1); + if (best) + pVGAModeInfo->pEnhTableEntry = best; /* Update mode CRTC info */ ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 8:0; @@ -696,12 +768,16 @@ vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) { ASTRecPtr pAST; - USHORT usTemp; + USHORT usTemp, ulPreCache = 0; UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE; pAST = ASTPTR(pScrn); jReg05 = jReg07 = jReg09 = jRegAC = jRegAD = jRegAE = 0; + /* init value */ + if ((pAST->jChipType == AST2500) && (pVGAModeInfo->pEnhTableEntry->Flags & AST2500PreCatchCRT)) + ulPreCache = 40; + /* unlock CRTC */ SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); @@ -719,10 +795,10 @@ if (usTemp & 0x20) jReg05 |= 0x80; /* HBE D[5] */ if (usTemp & 0x40) jRegAD |= 0x01; /* HBE D[6] */ SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F)); - usTemp = (mode->CrtcHSyncStart >> 3 ) - 1; + usTemp = ((mode->CrtcHSyncStart - ulPreCache) >> 3 ) - 1; if (usTemp & 0x100) jRegAC |= 0x40; /* HRS D[5] */ SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp)); - usTemp = ((mode->CrtcHSyncEnd >> 3 ) - 1) & 0x3F; + usTemp = (((mode->CrtcHSyncEnd - ulPreCache) >> 3 ) - 1) & 0x3F; if (usTemp & 0x20) jRegAD |= 0x04; /* HRE D[5] */ SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05)); @@ -762,6 +838,15 @@ SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09); SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80)); /* disable line compare */ + if ((pAST->jChipType == AST2500) && (pVGAModeInfo->pEnhTableEntry->Flags & AST2500PreCatchCRT)) + { + SetIndexRegMask(CRTC_PORT,0xB6, 0x3F, 0x80); + } + else + { + SetIndexRegMask(CRTC_PORT,0xB6, 0x3F, 0x00); + } + /* lock CRTC */ SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x80); @@ -790,14 +875,25 @@ pAST = ASTPTR(pScrn); pEnhModePtr = pVGAModeInfo->pEnhTableEntry; - if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2500) && (PCI_DEV_REVISION(pAST->PciInfo) > 0x40)) + pDCLKPtr = &DCLKTable_AST2500A1[pEnhModePtr->DCLKIndex]; + else if ((pAST->jChipType == AST2500) && (PCI_DEV_REVISION(pAST->PciInfo) == 0x40)) + pDCLKPtr = &DCLKTable_AST2500[pEnhModePtr->DCLKIndex]; + else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) pDCLKPtr = &DCLKTable_AST2100[pEnhModePtr->DCLKIndex]; else pDCLKPtr = &DCLKTable[pEnhModePtr->DCLKIndex]; SetIndexRegMask(CRTC_PORT,0xC0, 0x00, pDCLKPtr->Param1); SetIndexRegMask(CRTC_PORT,0xC1, 0x00, pDCLKPtr->Param2); - SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0x80) | ((pDCLKPtr->Param3 & 0x03) << 4) ); + if ((pAST->jChipType == AST2500) && (PCI_DEV_REVISION(pAST->PciInfo) == 0x40)) + { + SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0xF0)); + } + else + { + SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0xC0) | ((pDCLKPtr->Param3 & 0x03) << 4) ); + } } @@ -842,7 +938,7 @@ #endif /* Set Threshold */ - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) { SetIndexReg(CRTC_PORT,0xA7, 0x78); SetIndexReg(CRTC_PORT,0xA6, 0x60); @@ -870,9 +966,10 @@ pEnhModePtr = pVGAModeInfo->pEnhTableEntry; jReg = GetReg(MISC_PORT_READ); - jReg |= (UCHAR) (pEnhModePtr->Flags & SyncNN); + jReg &= ~0xC0; + if (pEnhModePtr->Flags & NVSync) jReg |= 0x80; + if (pEnhModePtr->Flags & NHSync) jReg |= 0x40; SetReg(MISC_PORT_WRITE,jReg); - } static Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/src/ast_mode.h new/xf86-video-ast-1.1.5/src/ast_mode.h --- old/xf86-video-ast-1.0.1/src/ast_mode.h 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/src/ast_mode.h 2015-08-19 03:24:48.000000000 +0200 @@ -66,14 +66,19 @@ #define HalfDCLK 0x00000002 #define DoubleScanMode 0x00000004 #define LineCompareOff 0x00000008 -#define SyncPP 0x00000000 -#define SyncPN 0x00000040 -#define SyncNP 0x00000080 -#define SyncNN 0x000000C0 #define HBorder 0x00000020 #define VBorder 0x00000010 -#define WideScreenMode 0x00000100 -#define NewModeInfo 0x00000200 +#define WideScreenMode 0x00000100 +#define NewModeInfo 0x00000200 +#define NHSync 0x00000400 +#define PHSync 0x00000800 +#define NVSync 0x00001000 +#define PVSync 0x00002000 +#define SyncPP (PVSync | PHSync) +#define SyncPN (PVSync | NHSync) +#define SyncNP (NVSync | PHSync) +#define SyncNN (NVSync | NHSync) +#define AST2500PreCatchCRT 0x00004000 /* DAC Definition */ #define DAC_NUM_TEXT 64 diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/xf86-video-ast-1.0.1/src/ast_vgatool.c new/xf86-video-ast-1.1.5/src/ast_vgatool.c --- old/xf86-video-ast-1.0.1/src/ast_vgatool.c 2014-08-08 10:59:04.000000000 +0200 +++ new/xf86-video-ast-1.1.5/src/ast_vgatool.c 2015-08-19 03:24:48.000000000 +0200 @@ -446,7 +446,7 @@ pAST->ulDRAMBusWidth = 32; /* Get DRAM Type */ - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) { switch (ulData & 0x03) { @@ -576,7 +576,7 @@ /* Modify DARM utilization to 60% for AST1100/2100 16bits DRAM, ycchen@032508 */ if ( ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150)) && (ulDRAMBusWidth == 16) ) DRAMEfficiency = 600; - else if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + else if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) DRAMEfficiency = 400; ulDRAMBandwidth = ulMCLK * ulDRAMBusWidth * 2 / 8; ActualDRAMBandwidth = ulDRAMBandwidth * DRAMEfficiency / 1000; @@ -605,7 +605,7 @@ } /* Add for AST2100, ycchen@061807 */ - if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST1180) ) + if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500) || (pAST->jChipType == AST1180) ) { if (ulDCLK > 200) ulDCLK = 200; } @@ -670,7 +670,7 @@ if (jReg & 0x80) pAST->jTxChipType = Tx_Sil164; /* Get 3rd Tx Info from BMC Scratch */ - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) { GetIndexRegMask(CRTC_PORT, 0xD1, 0x0E, jReg); switch (jReg) @@ -1117,7 +1117,7 @@ } /* Set Ext. Reg */ - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) { if (PCI_DEV_REVISION(pAST->PciInfo) > 0x20) pjExtRegInfo = ExtRegInfo_AST2300; @@ -1145,12 +1145,28 @@ /* Enable RAMDAC for A1, ycchen@113005 */ jReg = 0x04; - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2400)) jReg |= 0x20; SetIndexRegMask(CRTC_PORT,0xB6, 0xFF, jReg); } +static void vSetDefVCLK(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + + if ((pAST->jChipType == AST2500) && (PCI_DEV_REVISION(pAST->PciInfo) == 0x40)) + { + SetIndexRegMask(CRTC_PORT, 0xbc, 0x00, 0x40); + SetIndexRegMask(CRTC_PORT, 0xbd, 0x00, 0x38); + SetIndexRegMask(CRTC_PORT, 0xbe, 0x00, 0x3a); + SetIndexRegMask(CRTC_PORT, 0xbf, 0x00, 0x38); + SetIndexRegMask(CRTC_PORT, 0xcf, 0x00, 0x70); + SetIndexRegMask(CRTC_PORT, 0xb5, 0x00, 0xa8); + SetIndexRegMask(CRTC_PORT, 0xbb, 0x00, 0x43); + } +} + /* * AST2100/2150 DLL CBR Setting */ @@ -2908,12 +2924,485 @@ } /* vInitAST2300DRAMReg */ +/* + * AST2500 DRAM settings modules + */ +#define REGTBL_NUM 17 +#define REGIDX_010 0 +#define REGIDX_014 1 +#define REGIDX_018 2 +#define REGIDX_020 3 +#define REGIDX_024 4 +#define REGIDX_02C 5 +#define REGIDX_030 6 +#define REGIDX_214 7 +#define REGIDX_2E0 8 +#define REGIDX_2E4 9 +#define REGIDX_2E8 10 +#define REGIDX_2EC 11 +#define REGIDX_2F0 12 +#define REGIDX_2F4 13 +#define REGIDX_2F8 14 +#define REGIDX_RFC 15 +#define REGIDX_PLL 16 + +ULONG ddr3_1600_timing_table[REGTBL_NUM] = { +0x64604D38, /* 0x010 */ +0x29690599, /* 0x014 */ +0x00000300, /* 0x018 */ +0x00000000, /* 0x020 */ +0x00000000, /* 0x024 */ +0x02181E70, /* 0x02C */ +0x00000040, /* 0x030 */ +0x00000024, /* 0x214 */ +0x02001300, /* 0x2E0 */ +0x0E0000A0, /* 0x2E4 */ +0x000E001B, /* 0x2E8 */ +0x35B8C105, /* 0x2EC */ +0x08090408, /* 0x2F0 */ +0x9B000800, /* 0x2F4 */ +0x0E400A00, /* 0x2F8 */ +0x9971452F, /* tRFC */ +0x000071C1}; /* PLL */ + +ULONG ddr4_1600_timing_table[REGTBL_NUM] = { +0x63604E37, /* 0x010 */ +0xE97AFA99, /* 0x014 */ +0x00019000, /* 0x018 */ +0x08000000, /* 0x020 */ +0x00000400, /* 0x024 */ +0x00000410, /* 0x02C */ +0x00000101, /* 0x030 */ +0x00000024, /* 0x214 */ +0x03002900, /* 0x2E0 */ +0x0E0000A0, /* 0x2E4 */ +0x000E001C, /* 0x2E8 */ +0x35B8C106, /* 0x2EC */ +0x08080607, /* 0x2F0 */ +0x9B000900, /* 0x2F4 */ +0x0E400A00, /* 0x2F8 */ +0x99714545, /* tRFC */ +0x000071C1}; /* PLL */ + +static int MMCTestBurst_AST2500(ScrnInfoPtr pScrn, ULONG datagen) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG data, timecnt; + + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x000000C1 | (datagen << 3)); + timecnt = 0; + do{ + data = MIndwm(mmiobase, 0x1E6E0070) & 0x3000; + if(data & 0x2000){ + return(0); + } + if(++timecnt > TIMEOUT){ + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(0); + } + }while(!data); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(1); +} + +static int MMCTestSingle_AST2500(ScrnInfoPtr pScrn, ULONG datagen) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG data, timecnt; + + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000085 | (datagen << 3)); + timecnt = 0; + do{ + data = MIndwm(mmiobase, 0x1E6E0070) & 0x3000; + if(data & 0x2000){ + return(0); + } + if(++timecnt > TIMEOUT){ + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(0); + } + }while(!data); + MOutdwm(mmiobase, 0x1E6E0070, 0x00000000); + return(1); +} + +static ULONG CBRTest_AST2500(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + + MOutdwm(mmiobase, 0x1E6E0074, 0x0000FFFF); + MOutdwm(mmiobase, 0x1E6E007C, 0xFF00FF00); + if(!MMCTestBurst_AST2500(pScrn, 0)) return(0); + if(!MMCTestSingle_AST2500(pScrn, 0)) return(0); + return(1); +} + +static void DDR_Init_Common(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + + MOutdwm(mmiobase, 0x1E6E0034,0x00020080); + MOutdwm(mmiobase, 0x1E6E0008,0x2003000F); + MOutdwm(mmiobase, 0x1E6E0038,0x00000FFF); + MOutdwm(mmiobase, 0x1E6E0040,0x88448844); + MOutdwm(mmiobase, 0x1E6E0044,0x24422288); + MOutdwm(mmiobase, 0x1E6E0048,0x22222222); + MOutdwm(mmiobase, 0x1E6E004C,0x22222222); + MOutdwm(mmiobase, 0x1E6E0050,0x80000000); + MOutdwm(mmiobase, 0x1E6E0208,0x00000000); + MOutdwm(mmiobase, 0x1E6E0218,0x00000000); + MOutdwm(mmiobase, 0x1E6E0220,0x00000000); + MOutdwm(mmiobase, 0x1E6E0228,0x00000000); + MOutdwm(mmiobase, 0x1E6E0230,0x00000000); + MOutdwm(mmiobase, 0x1E6E02A8,0x00000000); + MOutdwm(mmiobase, 0x1E6E02B0,0x00000000); + MOutdwm(mmiobase, 0x1E6E0240,0x86000000); + MOutdwm(mmiobase, 0x1E6E0244,0x00008600); + MOutdwm(mmiobase, 0x1E6E0248,0x80000000); + MOutdwm(mmiobase, 0x1E6E024C,0x80808080); +} + +static void Do_DDRPHY_Init(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG data, pass, timecnt; + + pass = 0; + MOutdwm(mmiobase, 0x1E6E0060,0x00000005); + while(!pass){ + for(timecnt = 0;timecnt < TIMEOUT;timecnt++){ + data = MIndwm(mmiobase, 0x1E6E0060) & 0x1; + if(!data){ + break; + } + } + if(timecnt != TIMEOUT){ + data = MIndwm(mmiobase, 0x1E6E0300) & 0x000A0000; + if(!data){ + pass = 1; + } + } + if(!pass){ + MOutdwm(mmiobase, 0x1E6E0060,0x00000000); + usleep(10); /* delay 10 us */ + MOutdwm(mmiobase, 0x1E6E0060,0x00000005); + } + } + + MOutdwm(mmiobase, 0x1E6E0060,0x00000006); +} + +/****************************************************************************** + Check DRAM Size + 1Gb : 0x80000000 ~ 0x87FFFFFF + 2Gb : 0x80000000 ~ 0x8FFFFFFF + 4Gb : 0x80000000 ~ 0x9FFFFFFF + 8Gb : 0x80000000 ~ 0xBFFFFFFF + *****************************************************************************/ +static void Check_DRAM_Size(ScrnInfoPtr pScrn, ULONG tRFC) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG reg_04, reg_14; + + reg_04 = MIndwm(mmiobase, 0x1E6E0004) & 0xfffffffc; + reg_14 = MIndwm(mmiobase, 0x1E6E0014) & 0xffffff00; + + MOutdwm(mmiobase, 0xA0100000, 0x41424344); + MOutdwm(mmiobase, 0x90100000, 0x35363738); + MOutdwm(mmiobase, 0x88100000, 0x292A2B2C); + MOutdwm(mmiobase, 0x80100000, 0x1D1E1F10); + + /* Check 8Gbit */ + if(MIndwm(mmiobase, 0xA0100000) == 0x41424344){ + reg_04 |= 0x03; + reg_14 |= (tRFC >> 24) & 0xFF; + /* Check 4Gbit */ + }else if(MIndwm(mmiobase, 0x90100000) == 0x35363738){ + reg_04 |= 0x02; + reg_14 |= (tRFC >> 16) & 0xFF; + /* Check 2Gbit */ + }else if(MIndwm(mmiobase, 0x88100000) == 0x292A2B2C){ + reg_04 |= 0x01; + reg_14 |= (tRFC >> 8) & 0xFF; + }else{ + reg_14 |= tRFC & 0xFF; + } + MOutdwm(mmiobase, 0x1E6E0004, reg_04); + MOutdwm(mmiobase, 0x1E6E0014, reg_14); +} + +static void Enable_Cache(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG reg_04, data; + + reg_04 = MIndwm(mmiobase, 0x1E6E0004); + MOutdwm(mmiobase, 0x1E6E0004, reg_04 | 0x1000); + + do{ + data = MIndwm(mmiobase, 0x1E6E0004); + }while(!(data & 0x80000)); + MOutdwm(mmiobase, 0x1E6E0004, reg_04 | 0x400); +} + +static void Set_MPLL(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG addr, data, param; + + /* Reset MMC */ + MOutdwm(mmiobase, 0x1E6E0000,0xFC600309); + MOutdwm(mmiobase, 0x1E6E0034,0x00020080); + for(addr = 0x1e6e0004;addr < 0x1e6e0090;){ + MOutdwm(mmiobase, addr, 0x0); + addr += 4; + } + MOutdwm(mmiobase, 0x1E6E0034,0x00020000); + + MOutdwm(mmiobase, 0x1E6E2000, 0x1688A8A8); + data = MIndwm(mmiobase, 0x1E6E2070) & 0x00800000; + if(data){ /* CLKIN = 25MHz */ + param = 0x930023E0; + }else{ /* CLKIN = 24MHz */ + param = 0x93002400; + } + MOutdwm(mmiobase, 0x1E6E2020, param); + usleep(100); +} + +static void DDR3_Init_AST2500(ScrnInfoPtr pScrn, ULONG *ddr_table) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + + MOutdwm(mmiobase, 0x1E6E0004,0x00000303); + MOutdwm(mmiobase, 0x1E6E0010,ddr_table[REGIDX_010]); + MOutdwm(mmiobase, 0x1E6E0014,ddr_table[REGIDX_014]); + MOutdwm(mmiobase, 0x1E6E0018,ddr_table[REGIDX_018]); + MOutdwm(mmiobase, 0x1E6E0020,ddr_table[REGIDX_020]); /* MODEREG4/6 */ + MOutdwm(mmiobase, 0x1E6E0024,ddr_table[REGIDX_024]); /* MODEREG5 */ + MOutdwm(mmiobase, 0x1E6E002C,ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + MOutdwm(mmiobase, 0x1E6E0030,ddr_table[REGIDX_030]); /* MODEREG1/3 */ + + /* DDR PHY Setting */ + MOutdwm(mmiobase, 0x1E6E0200,0x02492AAE); + MOutdwm(mmiobase, 0x1E6E0204,0x00001001); + MOutdwm(mmiobase, 0x1E6E020C,0x55E00B0B); + MOutdwm(mmiobase, 0x1E6E0210,0x20000000); + MOutdwm(mmiobase, 0x1E6E0214,ddr_table[REGIDX_214]); + MOutdwm(mmiobase, 0x1E6E02E0,ddr_table[REGIDX_2E0]); + MOutdwm(mmiobase, 0x1E6E02E4,ddr_table[REGIDX_2E4]); + MOutdwm(mmiobase, 0x1E6E02E8,ddr_table[REGIDX_2E8]); + MOutdwm(mmiobase, 0x1E6E02EC,ddr_table[REGIDX_2EC]); + MOutdwm(mmiobase, 0x1E6E02F0,ddr_table[REGIDX_2F0]); + MOutdwm(mmiobase, 0x1E6E02F4,ddr_table[REGIDX_2F4]); + MOutdwm(mmiobase, 0x1E6E02F8,ddr_table[REGIDX_2F8]); + MOutdwm(mmiobase, 0x1E6E0290,0x00100008); + MOutdwm(mmiobase, 0x1E6E02C0,0x00000006); + + /* Controller Setting */ + MOutdwm(mmiobase, 0x1E6E0034,0x00020091); + + /* Wait DDR PHY init done */ + Do_DDRPHY_Init(pScrn); + + MOutdwm(mmiobase, 0x1E6E0120,ddr_table[REGIDX_PLL]); + MOutdwm(mmiobase, 0x1E6E000C,0x42AA5C81); + MOutdwm(mmiobase, 0x1E6E0034,0x0001AF93); + + Check_DRAM_Size(pScrn, ddr_table[REGIDX_RFC]); + Enable_Cache(pScrn); + MOutdwm(mmiobase, 0x1E6E001C,0x00000008); + MOutdwm(mmiobase, 0x1E6E0038,0xFFFFFF00); +} + +static void DDR4_Init_AST2500(ScrnInfoPtr pScrn, ULONG *ddr_table) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG data, data2, pass; + ULONG ddr_vref, phy_vref; + ULONG min_ddr_vref, min_phy_vref; + ULONG max_ddr_vref, max_phy_vref; + + MOutdwm(mmiobase, 0x1E6E0004,0x00000313); + MOutdwm(mmiobase, 0x1E6E0010,ddr_table[REGIDX_010]); + MOutdwm(mmiobase, 0x1E6E0014,ddr_table[REGIDX_014]); + MOutdwm(mmiobase, 0x1E6E0018,ddr_table[REGIDX_018]); + MOutdwm(mmiobase, 0x1E6E0020,ddr_table[REGIDX_020]); /* MODEREG4/6 */ + MOutdwm(mmiobase, 0x1E6E0024,ddr_table[REGIDX_024]); /* MODEREG5 */ + MOutdwm(mmiobase, 0x1E6E002C,ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ + MOutdwm(mmiobase, 0x1E6E0030,ddr_table[REGIDX_030]); /* MODEREG1/3 */ + + /* DDR PHY Setting */ + MOutdwm(mmiobase, 0x1E6E0200,0x42492AAE); + MOutdwm(mmiobase, 0x1E6E0204,0x09002000); + MOutdwm(mmiobase, 0x1E6E020C,0x55E00B0B); + MOutdwm(mmiobase, 0x1E6E0210,0x20000000); + MOutdwm(mmiobase, 0x1E6E0214,ddr_table[REGIDX_214]); + MOutdwm(mmiobase, 0x1E6E02E0,ddr_table[REGIDX_2E0]); + MOutdwm(mmiobase, 0x1E6E02E4,ddr_table[REGIDX_2E4]); + MOutdwm(mmiobase, 0x1E6E02E8,ddr_table[REGIDX_2E8]); + MOutdwm(mmiobase, 0x1E6E02EC,ddr_table[REGIDX_2EC]); + MOutdwm(mmiobase, 0x1E6E02F0,ddr_table[REGIDX_2F0]); + MOutdwm(mmiobase, 0x1E6E02F4,ddr_table[REGIDX_2F4]); + MOutdwm(mmiobase, 0x1E6E02F8,ddr_table[REGIDX_2F8]); + MOutdwm(mmiobase, 0x1E6E0290,0x00100008); + MOutdwm(mmiobase, 0x1E6E02C4,0x3C183C3C); + MOutdwm(mmiobase, 0x1E6E02C8,0x00631E0E); + + /* Controller Setting */ + MOutdwm(mmiobase, 0x1E6E0034,0x0001A991); + + /* Train PHY Vref first */ + min_phy_vref = max_phy_vref = 0x0; + pass = 0; + MOutdwm(mmiobase, 0x1E6E02C0,0x00001C06); + for(phy_vref = 0x40;phy_vref < 0x80;phy_vref++){ + MOutdwm(mmiobase, 0x1E6E000C,0x00000000); + MOutdwm(mmiobase, 0x1E6E0060,0x00000000); + MOutdwm(mmiobase, 0x1E6E02CC,phy_vref | (phy_vref << 8)); + /* Fire DFI Init */ + Do_DDRPHY_Init(pScrn); + MOutdwm(mmiobase, 0x1E6E000C,0x00005C01); + if(CBRTest_AST2500(pScrn)){ + pass++; + data = MIndwm(mmiobase, 0x1E6E03D0); + data2 = data >> 8; + data = data & 0xff; + if(data > data2){ + data = data2; + } + + if(max_phy_vref < data){ + max_phy_vref = data; + min_phy_vref = phy_vref; + } + }else if(pass > 0){ + break; + } + } + MOutdwm(mmiobase, 0x1E6E02CC,min_phy_vref | (min_phy_vref << 8)); + + /* Train DDR Vref next */ + min_ddr_vref = 0xFF; + max_ddr_vref = 0x0; + pass = 0; + for(ddr_vref = 0x00;ddr_vref < 0x40;ddr_vref++){ + MOutdwm(mmiobase, 0x1E6E000C,0x00000000); + MOutdwm(mmiobase, 0x1E6E0060,0x00000000); + MOutdwm(mmiobase, 0x1E6E02C0,0x00000006 | (ddr_vref << 8)); + /* Fire DFI Init */ + Do_DDRPHY_Init(pScrn); + MOutdwm(mmiobase, 0x1E6E000C,0x00005C01); + if(CBRTest_AST2500(pScrn)){ + pass++; + if(min_ddr_vref > ddr_vref){ + min_ddr_vref = ddr_vref; + } + if(max_ddr_vref < ddr_vref){ + max_ddr_vref = ddr_vref; + } + }else if(pass != 0){ + break; + } + } + MOutdwm(mmiobase, 0x1E6E000C,0x00000000); + MOutdwm(mmiobase, 0x1E6E0060,0x00000000); + ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1; + MOutdwm(mmiobase, 0x1E6E02C0,0x00000006 | (ddr_vref << 8)); + + /* Wait DDR PHY init done */ + Do_DDRPHY_Init(pScrn); + + MOutdwm(mmiobase, 0x1E6E0120,ddr_table[REGIDX_PLL]); + MOutdwm(mmiobase, 0x1E6E000C,0x42AA5C81); + MOutdwm(mmiobase, 0x1E6E0034,0x0001AF93); + + Check_DRAM_Size(pScrn, ddr_table[REGIDX_RFC]); + Enable_Cache(pScrn); + MOutdwm(mmiobase, 0x1E6E001C,0x00000008); + MOutdwm(mmiobase, 0x1E6E0038,0xFFFFFF00); +} + +static int DRAM_Init_AST2500(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + UCHAR *mmiobase = pAST->MMIOVirtualAddr; + ULONG data; + + Set_MPLL(pScrn); + DDR_Init_Common(pScrn); + data = MIndwm(mmiobase, 0x1E6E2070); + if(data & 0x01000000){ + DDR4_Init_AST2500(pScrn, ddr4_1600_timing_table); + }else{ + DDR3_Init_AST2500(pScrn, ddr3_1600_timing_table); + } + MOutdwm(mmiobase, 0x1E6E2040, MIndwm(mmiobase, 0x1E6E2040) | 0x41); + /* Patch code */ + data = MIndwm(mmiobase, 0x1E6E200C) & 0xF9FFFFFF; + MOutdwm(mmiobase, 0x1E6E200C, data | 0x10000000); + return(1); +} + +static void vInitAST2500DRAMReg(ScrnInfoPtr pScrn) +{ + ASTRecPtr pAST = ASTPTR(pScrn); + ULONG ulTemp; + UCHAR jReg; + + GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg); + + if ((jReg & 0x80) == 0) /* VGA only */ + { + *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000; + *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1; + + *(ULONG *) (pAST->MMIOVirtualAddr + 0x12000) = 0x1688A8A8; + do { + ; + } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x12000) != 0x01); + + *(ULONG *) (pAST->MMIOVirtualAddr + 0x10000) = 0xFC600309; + do { + ; + } while (*(volatile ULONG *) (pAST->MMIOVirtualAddr + 0x10000) != 0x01); + + /* Slow down CPU/AHB CLK in VGA only mode */ + ulTemp = *(ULONG *) (pAST->MMIOVirtualAddr + 0x12008); + ulTemp |= 0x73; + *(ULONG *) (pAST->MMIOVirtualAddr + 0x12008) = ulTemp; + + DRAM_Init_AST2500(pScrn); + + ulTemp = MIndwm(pAST->MMIOVirtualAddr, 0x1E6E2040); + MOutdwm(pAST->MMIOVirtualAddr, 0x1E6E2040, ulTemp | 0x40); + } + + /* wait ready */ + do { + GetIndexRegMask(CRTC_PORT, 0xD0, 0xFF, jReg); + } while ((jReg & 0x40) == 0); + +} /* vInitAST2500DRAMReg */ + void static vGetDefaultSettings(ScrnInfoPtr pScrn) { ASTRecPtr pAST = ASTPTR(pScrn); ULONG ulData; - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) { *(ULONG *) (pAST->MMIOVirtualAddr + 0xF004) = 0x1e6e0000; *(ULONG *) (pAST->MMIOVirtualAddr + 0xF000) = 0x1; @@ -3020,7 +3509,7 @@ UCHAR jReg; /* Only support on AST2300/2400 */ - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400) || (pAST->jChipType == AST2500)) { GetIndexRegMask(CRTC_PORT, 0xD1, 0xFF, jReg); /* D[1]: DVO Enable */ switch (jReg & 0x0E) /* D[11:9] */ @@ -3069,12 +3558,15 @@ vEnableVGA(pScrn); vASTOpenKey(pScrn); + vSetDefVCLK(pScrn); vSetDefExtReg(pScrn); if (Flags == 0) vGetDefaultSettings(pScrn); - if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) + if (pAST->jChipType == AST2500) + vInitAST2500DRAMReg(pScrn); + else if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) vInitAST2300DRAMReg(pScrn); else vInitDRAMReg(pScrn); @@ -3444,7 +3936,7 @@ void vASTEnableVGAMMIO(ScrnInfoPtr pScrn) { ASTRecPtr pAST = ASTPTR(pScrn); - ULONG ulData; + uint32_t ulData; UCHAR jReg; jReg = inb(pAST->RelocateIO + 0x43);
