Hello community, here is the log from the commit of package iverilog for openSUSE:Factory checked in at 2016-03-26 15:25:46 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/iverilog (Old) and /work/SRC/openSUSE:Factory/.iverilog.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "iverilog" Changes: -------- --- /work/SRC/openSUSE:Factory/iverilog/iverilog.changes 2014-02-15 08:05:22.000000000 +0100 +++ /work/SRC/openSUSE:Factory/.iverilog.new/iverilog.changes 2016-03-26 15:25:50.000000000 +0100 @@ -1,0 +2,12 @@ +Mon Mar 21 20:43:34 UTC 2016 - dmitr...@opensuse.org + +- Update to version 10.1 + * No changelog available + +------------------------------------------------------------------- +Fri Nov 20 14:44:23 UTC 2015 - dmitr...@opensuse.org + +- Update to version 10.0 + * No changelog available + +------------------------------------------------------------------- Old: ---- verilog-0.9.7.tar.gz New: ---- verilog-10.1.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ iverilog.spec ++++++ --- /var/tmp/diff_new_pack.cB4Qe3/_old 2016-03-26 15:25:51.000000000 +0100 +++ /var/tmp/diff_new_pack.cB4Qe3/_new 2016-03-26 15:25:51.000000000 +0100 @@ -1,7 +1,7 @@ # # spec file for package iverilog # -# Copyright (c) 2014 SUSE LINUX Products GmbH, Nuernberg, Germany. +# Copyright (c) 2016 SUSE LINUX GmbH, Nuernberg, Germany. # # All modifications and additions to the file contributed by third parties # remain the property of their copyright owners, unless otherwise agreed @@ -17,23 +17,22 @@ Name: iverilog +Version: 10.1 +Release: 0 +%define major_ver 10 Summary: Simulation and synthesis tool for IEEE-1364 License: GPL-2.0+ Group: Productivity/Scientific/Electronics -Version: 0.9.7 -Release: 0 Url: http://iverilog.icarus.com/ - -BuildRoot: %{_tmppath}/%{name}-%{version}-build - -Source: ftp://icarus.com/pub/eda/verilog/v0.9/verilog-%{version}.tar.gz - +Source: ftp://icarus.com/pub/eda/verilog/v%{major_ver}/verilog-%{version}.tar.gz BuildRequires: bison +BuildRequires: fdupes BuildRequires: flex BuildRequires: gcc-c++ BuildRequires: gperf BuildRequires: readline-devel BuildRequires: zlib-devel +BuildRoot: %{_tmppath}/%{name}-%{version}-build %description Icarus Verilog is a Verilog compiler that generates a variety of @@ -56,8 +55,9 @@ make %{?_smp_mflags} %install -%makeinstall +%make_install rm %{buildroot}/%{_libdir}/*.a +%fdupes -s %{buildroot}/%{_libdir}/ivl/ %check make check ++++++ verilog-0.9.7.tar.gz -> verilog-10.1.tar.gz ++++++ ++++ 202930 lines of diff (skipped)
