Michael Buesch wrote: > On Tuesday 01 July 2008 21:50:43 Steve Brown wrote: > >> It looks like (almost) every other phy register doesn't respond. I put >> in a large (200us) delay between accesses with no change in behaviour. >> If it is timing, it must be on the pci bus side of the core. >> > > Ah this is a minipci card? > Can you try to play with the PCI bus timings that are initialised in > the PCI-core driver of SSB? See the function that initialises the > PCI-core in hostmode. > > The problem is actually in b44. The ssb_pcicore_dev_irqvecs_enable call in b44_chip_enable at b44.c:1281 is the cause of the problem. It gets called unconditionally, even if the b44 is not on the pci. With it commented out, b43 loads, loads firmware and returns scan results.
It crept in sometime after 2.6.23.1. I'm not familiar with b44 and can't offer a fix. I still don't understand how this caused the bus errors. Anybody got an explanation? Steve _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org http://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
