Hi,
Sorry for many garbage chars in last patch mail. Hope this one has no problem.
Last time I submitted a patch for AR7242 and PB92 but it was not
accepted. I guessed maybe the reason is because of invalid mail
format, so re-submit it again with format revised. This time only
AR7242's Ethernet setting is involved. I will appreciate if anybody
can point out the problem in this patch or this mail.
AR7242 has one GMII/RGMII interface. It is different with
AR7240/AR7241 which have no MII interface.
The frequency of MDC can't be too high, like 50MHz, otherwise AR71xx
would have problem to communicate with external switch devices.
Signed-off-by: Jess Zhu <jess....@gmail.com>
Modified:
Index:
trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
Index: trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
-------------------------------
Index:
trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
===================================================================
--- trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
(revision
24814)
+++ trunk/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
(working
copy)
@@ -152,6 +152,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2C
+
#define AR91XX_PLL_REG_CPU_CONFIG 0x00
#define AR91XX_PLL_REG_ETH_CONFIG 0x04
#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
Index: trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c
===================================================================
--- trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c (revision 24814)
+++ trunk/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c (working copy)
@@ -94,7 +94,6 @@
ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
break;
case AR71XX_SOC_AR7242:
- ar71xx_mdio_data.is_ar7240 = 1;
break;
default:
break;
@@ -196,6 +195,19 @@
/* TODO */
}
+static void ar7242_set_pll_ge0(int speed)
+{
+ u32 val = ar71xx_get_eth_pll(0, speed);
+
+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK,
+ val, AR71XX_ETH0_PLL_SHIFT);
+}
+
+static void ar7242_set_pll_ge1(int speed)
+{
+ /* TODO */
+}
+
static void ar91xx_set_pll_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
@@ -316,6 +328,10 @@
#define AR724X_PLL_VAL_100 0x00001099
#define AR724X_PLL_VAL_10 0x00991099
+#define AR7242_PLL_VAL_1000 0x16000000
+#define AR7242_PLL_VAL_100 0x00000101
+#define AR7242_PLL_VAL_10 0x00001616
+
#define AR91XX_PLL_VAL_1000 0x1a000000
#define AR91XX_PLL_VAL_100 0x13000a44
#define AR91XX_PLL_VAL_10 0x00441099
@@ -347,11 +363,16 @@
case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241:
- case AR71XX_SOC_AR7242:
pll_10 = AR724X_PLL_VAL_10;
pll_100 = AR724X_PLL_VAL_100;
pll_1000 = AR724X_PLL_VAL_1000;
break;
+
+ case AR71XX_SOC_AR7242:
+ pll_10 = AR7242_PLL_VAL_10;
+ pll_100 = AR7242_PLL_VAL_100;
+ pll_1000 = AR7242_PLL_VAL_1000;
+ break;
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
@@ -443,7 +464,6 @@
break;
case AR71XX_SOC_AR7241:
- case AR71XX_SOC_AR7242:
ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
/* fall through */
@@ -462,6 +482,25 @@
pdata->fifo_cfg3 = 0x01f00140;
break;
+ case AR71XX_SOC_AR7242:
+ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
+ : ar724x_ddr_flush_ge0;
+ pdata->set_pll = id ? ar7242_set_pll_ge1
+ : ar7242_set_pll_ge0;
+ pdata->is_ar724x = 1;
+
+ if (!pdata->fifo_cfg1)
+ pdata->fifo_cfg1 = 0x0010ffff;
+ if (!pdata->fifo_cfg2)
+ pdata->fifo_cfg2 = 0x015500aa;
+ if (!pdata->fifo_cfg3)
+ pdata->fifo_cfg3 = 0x01f00140;
+
+ pdata->has_gbit = 1;
+ break;
+
+
case AR71XX_SOC_AR9130:
pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
: ar91xx_ddr_flush_ge0;
_______________________________________________
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/mailman/listinfo/openwrt-devel
