On 13 February 2014 22:45, Roman Yeryomin <leroi.li...@gmail.com> wrote: > On 13 February 2014 21:32, Mikko Hissa <mikko.hi...@werzek.com> wrote: >> On 01 Feb 2014, at 02:08, Roman Yeryomin <leroi.li...@gmail.com> wrote: >> >> Hello everybody! >> I'm trying to get mt7620 (ramips target, rt-n14u board) wifi working >> but no luck. I have ported init functions and channel setup from the >> original (known to be working) driver. The original driver (and >> datasheet) is available in the web. >> Unfortunately I have no experience in wifi drivers and this is my >> first one. Even worse I don't know what those register (rfcsr and bbp) >> writes _should_ do because they are not in datasheet (I suppose the >> earlier chips rf registers are not documented also). >> Attaching the patches hoping somebody with more experience could help >> or at least give an advise. The patches are not very clean and >> probably some things can be done in a different way but that's not the >> point right now. >> >> >> I took a quick look at your patches and one thing caught my eye... >> In rt2800.h you have: >> +#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x00ff0000) >> 8bit mask for register number AND bank id? I think it should be 2ff (10bits) >> because >> >> >> That 2ff should, of course, be 3ff. >> >> in rfcsr_write you are doing: >> + rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, >> word); >> where the word contains up to 6bits of register number AND 4bits of bank id. >> So those writes above bank no. 3 are not happening. >> >> >> Wow, indeed it should be 3ff (10 bits like you said). Thanks for the >> find! I will try it today... >> >> >> So it made it a bit better - tx and interrupt counter increments much >> faster but still nothing in the air and rx counter stays zero. >> Also nothing in monitor mode. :( >> Any other ideas? >> >> >> A wild guess here is that the PLL is way off. I see that you use >> spec->clk_is_20mhz in config_channel. >> I think, that this was added for RT3352 which has the bit 20 set in the >> register SYSCTL_BASE+0x10 if 20Mhz clock source is used. MT7620 uses bit 6 >> for the same thing. If you look at arch/mips/ralink/mt7620.c wmac_clk is not >> defined at all. Try forcing spec->clk_is_20mhz to true and see if it helps! >> >> >> I missed that you did set the wmac clock to 40Mhz in mt7620.c, which isn’t >> correct. It should be set according to the SYSC_REG_SYSTEM_CONFIG0 register >> bit 6! > > Yea.. I tried both 20 and 40 but that was before you found the incorrect mask. > Let me try 20MHz...
Seems setting it to 20MHz didn't change anything. But you are right, I will make it read the setting from the register to get rid of uncertainty in further tests. Regards, Roman _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
