No logic changes of qca956x. Just move the eth changes out of the 735 patch to 'dev-eth.c' file.
Regards, Miaoqing -----Original Message----- From: Roman Yeryomin [mailto:leroi.li...@gmail.com] Sent: Thursday, July 02, 2015 4:55 PM To: Pan, Miaoqing Cc: OpenWrt Development List Subject: Re: [OpenWrt-Devel] [PATCH 1/2] ar71xx: rework patch for qca953x/956x On 2 July 2015 at 09:49, <miaoq...@qti.qualcomm.com> wrote: > From: Miaoqing Pan <miaoq...@codeaurora.org> > > Patch cherry-picked from the following location: > https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h > =release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c > 0e > > Changelist, > - add more register defines > - add EHCI support > - fix GPIO pin count to 18 > - fix chained irq disabled > - fix GMAC0/GMAC1 initial > - fix WMAC irq number to 47 > - merge the changes of dev-eth.c from the patch to file. > > Signed-off-by: Miaoqing Pan <miaoq...@codeaurora.org> > --- > .../linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 18 +- > ...07-MIPS-ath79-add-support-for-QCA953x-SoC.patch | 352 > +++++++++++++++++---- ...35-MIPS-ath79-add-support-for-QCA956x-SoC.patch | > 183 ++++------- > .../736-MIPS-ath79-fix-chained-irq-disable.patch | 21 +- > 4 files changed, 387 insertions(+), 187 deletions(-) > > diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c > b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c > index ae3db4c..ff94e2e 100644 > --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c > +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c > @@ -198,6 +198,8 @@ void __init ath79_register_mdio(unsigned int id, u32 > phy_mask) > case ATH79_SOC_AR9330: > case ATH79_SOC_AR9331: > case ATH79_SOC_QCA9533: > + case ATH79_SOC_QCA9561: > + case ATH79_SOC_TP9343: > mdio_dev = &ath79_mdio1_device; > mdio_data = &ath79_mdio1_data; > break; > @@ -256,6 +258,8 @@ void __init ath79_register_mdio(unsigned int id, u32 > phy_mask) > break; > > case ATH79_SOC_QCA9533: > + case ATH79_SOC_QCA9561: > + case ATH79_SOC_TP9343: > mdio_data->builtin_switch = 1; > break; > > @@ -571,6 +575,8 @@ static void __init ath79_init_eth_pll_data(unsigned int > id) > case ATH79_SOC_QCA9533: > case ATH79_SOC_QCA9556: > case ATH79_SOC_QCA9558: > + case ATH79_SOC_QCA9561: > + case ATH79_SOC_TP9343: > pll_10 = AR934X_PLL_VAL_10; > pll_100 = AR934X_PLL_VAL_100; > pll_1000 = AR934X_PLL_VAL_1000; @@ -627,6 +633,8 @@ > static int __init ath79_setup_phy_if_mode(unsigned int id, > case ATH79_SOC_AR9330: > case ATH79_SOC_AR9331: > case ATH79_SOC_QCA9533: > + case ATH79_SOC_QCA9561: > + case ATH79_SOC_TP9343: > pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; > break; > > @@ -687,7 +695,8 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, > case ATH79_SOC_AR7241: > case ATH79_SOC_AR9330: > case ATH79_SOC_AR9331: > - case ATH79_SOC_QCA9533: > + case ATH79_SOC_QCA9561: > + case ATH79_SOC_TP9343: > pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; > break; > > @@ -697,6 +706,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, > case ATH79_SOC_AR9341: > case ATH79_SOC_AR9342: > case ATH79_SOC_AR9344: > + case ATH79_SOC_QCA9533: > switch (pdata->phy_if_mode) { > case PHY_INTERFACE_MODE_MII: > case PHY_INTERFACE_MODE_GMII: > @@ -986,6 +996,7 @@ void __init ath79_register_eth(unsigned int id) > case ATH79_SOC_AR9341: > case ATH79_SOC_AR9342: > case ATH79_SOC_AR9344: > + case ATH79_SOC_QCA9533: > if (id == 0) { > pdata->reset_bit = AR934X_RESET_GE0_MAC | > AR934X_RESET_GE0_MDIO; @@ > -1017,7 +1028,8 @@ void __init ath79_register_eth(unsigned int id) > pdata->fifo_cfg3 = 0x01f00140; > break; > > - case ATH79_SOC_QCA9533: > + case ATH79_SOC_QCA9561: > + case ATH79_SOC_TP9343: > if (id == 0) { > pdata->reset_bit = AR933X_RESET_GE0_MAC | > AR933X_RESET_GE0_MDIO; @@ > -1123,6 +1135,8 @@ void __init ath79_register_eth(unsigned int id) > case ATH79_SOC_AR9330: > case ATH79_SOC_AR9331: > case ATH79_SOC_QCA9533: > + case ATH79_SOC_QCA9561: > + case ATH79_SOC_TP9343: > pdata->mii_bus_dev = &ath79_mdio1_device.dev; > break; > This will not work for e.g. qca9563 (which has the same id as QCA9561) because it has single ethernet MAC (GMAC0) which works in SGMII mode only. I have several patches regarding qca ethernet in my queue. Not sure they are correct for 100% cases but will submit them for evaluation. Regards, Roman _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel