check word sizes, set spi polarity and enable more buffer mode
Signed-off-by: Michael Lee <igv...@gmail.com>
---
...0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch | 35 +++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git
a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch
b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch
index 71eba30..0ea0508 100644
---
a/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch
+++
b/target/linux/ramips/patches-3.18/0061-SPI-ralink-add-mt7621-SoC-spi-driver.patch
@@ -25,7 +25,7 @@
obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
--- /dev/null
+++ b/drivers/spi/spi-mt7621.c
-@@ -0,0 +1,532 @@
+@@ -0,0 +1,565 @@
+/*
+ * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
+ *
@@ -167,6 +167,20 @@
+ iowrite32(val, rs->base + reg);
+}
+
++static inline void mt7621_spi_setbits(struct mt7621_spi *rs, u32 reg, u32
mask)
++{
++ void __iomem *addr = rs->base + reg;
++
++ iowrite32((ioread32(addr) | mask), addr);
++}
++
++static inline void mt7621_spi_clrbits(struct mt7621_spi *rs, u32 reg, u32
mask)
++{
++ void __iomem *addr = rs->base + reg;
++
++ iowrite32((ioread32(addr) & ~mask), addr);
++}
++
+static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
+{
+ u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
@@ -437,6 +451,7 @@
+static int mt7621_spi_setup(struct spi_device *spi)
+{
+ struct spi_master *master = spi->master;
++ struct mt7621_spi *rs = spi_master_get_devdata(master);
+
+ if ((spi->max_speed_hz > master->max_speed_hz) ||
+ (spi->max_speed_hz < master->min_speed_hz)) {
@@ -445,6 +460,24 @@
+ return -EINVAL;
+ }
+
++ if (!(master->bits_per_word_mask &
++ BIT(spi->bits_per_word - 1))) {
++ dev_err(&spi->dev, "invalide bits_per_word %d\n",
++ spi->bits_per_word);
++ return -EINVAL;
++ }
++
++ /* chip polarity */
++ if (spi->mode & SPI_CS_HIGH)
++ mt7621_spi_setbits(rs, MT7621_SPI_POLAR,
++ (SPIPOL_CSPOL_HIGH << spi->chip_select));
++ else
++ mt7621_spi_clrbits(rs, MT7621_SPI_POLAR,
++ (SPIPOL_CSPOL_HIGH << spi->chip_select));
++
++ /* enable more buffer mode */
++ mt7621_spi_setbits(rs, MT7621_SPI_MASTER, SPIMASTER_MB_MODE);
++
+ return 0;
+}
+
--
2.3.6
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