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Shouldn't the atheros phy additions be in their own patch? It
seems out of scope to just have it buried inside a "support xxxx"
with no further details in your commit comment.
More comments inline...
Sincerely,
Karl Palsson
Philippe DUCHEIN <wireless-...@duchein.net> wrote:
> This patch is for Wallys DR344 support under OpenWRT
>
> Signed-off-by: Philippe DUCHEIN <wireless-...@duchein.net>
>
> —
>
> diff -Nru a/target/linux/ar71xx/base-files/etc/diag.sh
> b/target/linux/ar71xx/base-files/etc/diag.sh
> --- a/target/linux/ar71xx/base-files/etc/diag.sh 2015-10-27
> 11:22:05.851103540 +0100
> +++ b/target/linux/ar71xx/base-files/etc/diag.sh 2015-10-27
> 11:27:41.138057656 +0100
> @@ -347,6 +347,9 @@
> wp543)
> status_led="wp543:green:diag"
> ;;
> + dr344)
> + status_led="dr344:green:status"
> + ;;
> wpj344)
> status_led="wpj344:green:status"
> ;;
> diff -Nru
> a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
> b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
> --- a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
> 2015-10-27 11:22:05.846103482 +0100
> +++ b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
> 2015-10-27 11:30:35.631113903 +0100
> @@ -404,6 +404,10 @@
> ucidef_set_interfaces_lan_wan "eth1" "eth0"
> ;;
>
> +dr344)
> + ucidef_set_interface_lan "eth0 eth1"
> + ;;
> +
There's a lot of precedent in this file for stacking entries,
even if they are from different vendors. Is there any reason not
to just add this to the set of devices at line 23 that have this
same networking configuration?
> wpj344)
> ucidef_set_interfaces_lan_wan "eth0.1" "eth0.2"
> ucidef_add_switch "switch0" "1" "1"
> diff -Nru a/target/linux/ar71xx/base-files/lib/ar71xx.sh
> b/target/linux/ar71xx/base-files/lib/ar71xx.sh
> --- a/target/linux/ar71xx/base-files/lib/ar71xx.sh 2015-10-27
> 11:22:05.874103812 +0100
> +++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh 2015-10-27
> 11:27:41.138057656 +0100
> @@ -889,6 +889,9 @@
> *WPJ344)
> name="wpj344"
> ;;
> + *DR344)
> + name="dr344"
> + ;;
This list is _mostly_ sorted alphabetically. There's definitely out of place
devices, but if you're adding new ones, why not add them in order? around line
450, by the Dragino board would seem to be the most appropriate place for this.
> *WPJ531)
> name="wpj531"
> ;;
> diff -Nru
> a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
> b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
> --- a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh 2015-10-27
> 11:22:05.862103670 +0100
> +++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh 2015-10-27
> 11:27:41.139057668 +0100
> @@ -240,6 +240,7 @@
> wpj531 | \
> wndap360 | \
> wpj344 | \
> + dr344 | \
Same here. It's not really relevant in this file that the wpj344
and this one are virtually the same.
> wzr-hp-g300nh2 | \
> wzr-hp-g300nh | \
> wzr-hp-g450h | \
> diff -Nru a/target/linux/ar71xx/config-4.1
> b/target/linux/ar71xx/config-4.1
> --- a/target/linux/ar71xx/config-4.1 2015-10-27 11:22:06.234108060 +0100
> +++ b/target/linux/ar71xx/config-4.1 2015-10-27 11:27:41.139057668 +0100
> @@ -18,6 +18,7 @@
> CONFIG_ARCH_SUSPEND_POSSIBLE=y
> CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
> CONFIG_AT803X_PHY=y
> +CONFIG_ATHEROS_PHY=y
> CONFIG_ATH79=y
> CONFIG_ATH79_DEV_AP9X_PCI=y
> CONFIG_ATH79_DEV_DSA=y
> @@ -158,6 +159,7 @@
> CONFIG_ATH79_MACH_WP543=y
> CONFIG_ATH79_MACH_WPE72=y
> CONFIG_ATH79_MACH_WPJ344=y
> +CONFIG_ATH79_MACH_DR344=y
> CONFIG_ATH79_MACH_WPJ531=y
> CONFIG_ATH79_MACH_WPJ558=y
> CONFIG_ATH79_MACH_WRT160NL=y
> diff -Nru
> a/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c
> b/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c
> --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c 1970-01-01
> 01:00:00.000000000 +0100
> +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c 2015-10-27
> 11:27:41.139057668 +0100
> @@ -0,0 +1,183 @@
> +/*
> + * Wallys DR344 board support
> + *
> + * Copyright (c) 2015 Philippe DUCHEIN <pduch...@gmail.com>
> + * Copyright (c) 2011 Qualcomm Atheros
> + * Copyright (c) 2011-2012 Gabor Juhos <juh...@openwrt.org>
> + *
> + * Permission to use, copy, modify, and/or distribute this software for any
> + * purpose with or without fee is hereby granted, provided that the above
> + * copyright notice and this permission notice appear in all copies.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
> + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
> + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
> + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
> + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
> + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
> + *
> + */
> +
> +#include <linux/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/ath9k_platform.h>
> +#include <linux/ar8216_platform.h>
> +
> +#include <asm/mach-ath79/ar71xx_regs.h>
> +
> +#include "common.h"
> +#include "pci.h"
> +#include "dev-ap9x-pci.h"
> +#include "dev-gpio-buttons.h"
> +#include "dev-eth.h"
> +#include "dev-usb.h"
> +#include "dev-leds-gpio.h"
> +#include "dev-m25p80.h"
> +#include "dev-spi.h"
> +#include "dev-wmac.h"
> +#include "machtypes.h"
> +
> +#define DR344_GPIO_LED_SIG1 15
> +#define DR344_GPIO_LED_SIG2 20
> +#define DR344_GPIO_LED_SIG3 21
> +#define DR344_GPIO_LED_SIG4 22
> +#define DR344_GPIO_EXTERNAL_LNA0 18
> +#define DR344_GPIO_EXTERNAL_LNA1 19
> +#define DR344_GPIO_LED_STATUS 14
> +
> +#define DR344_GPIO_BTN_RESET 12
> +
> +#define DR344_KEYS_POLL_INTERVAL 20 /* msecs */
> +#define DR344_KEYS_DEBOUNCE_INTERVAL (3 *
> DR344_KEYS_POLL_INTERVAL)
> +
> +#define DR344_MAC0_OFFSET 0
> +#define DR344_MAC1_OFFSET 6
> +#define DR344_WMAC_CALDATA_OFFSET 0x1000
> +#define DR344_PCIE_CALDATA_OFFSET 0x5000
> +
> +static struct gpio_led dr344_leds_gpio[] __initdata = {
> + {
> + .name = "dr344:green:status",
> + .gpio = DR344_GPIO_LED_STATUS,
> + .active_low = 1,
> + },
> + {
> + .name = "dr344:red:sig1",
> + .gpio = DR344_GPIO_LED_SIG1,
> + .active_low = 1,
> + },
> + {
> + .name = "dr344:yellow:sig2",
> + .gpio = DR344_GPIO_LED_SIG2,
> + .active_low = 1,
> + },
> + {
> + .name = "dr344:green:sig3",
> + .gpio = DR344_GPIO_LED_SIG3,
> + .active_low = 1,
> + },
> + {
> + .name = "dr344:green:sig4",
> + .gpio = DR344_GPIO_LED_SIG4,
> + .active_low = 1,
> + }
> +};
> +
> +static struct gpio_keys_button dr344_gpio_keys[] __initdata =
> {
> + {
> + .desc = "reset",
> + .type = EV_KEY,
> + .code = KEY_RESTART,
> + .debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL,
> + .gpio = DR344_GPIO_BTN_RESET,
> + .active_low = 1,
> + },
> +};
> +
> +static struct ar8327_pad_cfg dr344_ar8327_pad0_cfg = {
> + .mode = AR8327_PAD_MAC_RGMII,
> + .txclk_delay_en = true,
> + .rxclk_delay_en = true,
> + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
> + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
> +};
> +
> +static struct ar8327_led_cfg dr344_ar8327_led_cfg = {
> + .led_ctrl0 = 0x00000000,
> + .led_ctrl1 = 0xc737c737,
> + .led_ctrl2 = 0x00000000,
> + .led_ctrl3 = 0x00c30c00,
> + .open_drain = true,
> +};
> +
> +static struct ar8327_platform_data dr344_ar8327_data = {
> + .pad0_cfg = &dr344_ar8327_pad0_cfg,
> + .port0_cfg = {
> + .force_link = 1,
> + .speed = AR8327_PORT_SPEED_1000,
> + .duplex = 1,
> + .txpause = 1,
> + .rxpause = 1,
> + },
> + .led_cfg = &dr344_ar8327_led_cfg,
> +};
> +
> +static struct mdio_board_info dr344_mdio0_info[] = {
> + {
> + .bus_id = "ag71xx-mdio.0",
> + .phy_addr = 0,
> + .platform_data = &dr344_ar8327_data,
> + },
> +};
> +
> +static void __init dr344_setup(void)
> +{
> + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
> +
> + ath79_register_m25p80(NULL);
> + ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
> + dr344_leds_gpio);
> + ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
> + ARRAY_SIZE(dr344_gpio_keys),
> + dr344_gpio_keys);
> +
> + ath79_register_usb();
> + ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
> +
> +
> + ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
> +
> +
> + ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
> +
> + ath79_register_pci();
> +
> + mdiobus_register_board_info(dr344_mdio0_info,
> + ARRAY_SIZE(dr344_mdio0_info));
> +
> + ath79_register_mdio(1, 0x0);
> + ath79_register_mdio(0, 0x0);
> +
> + ath79_init_mac(ath79_eth0_data.mac_addr, art + DR344_MAC0_OFFSET, 0);
> + ath79_init_mac(ath79_eth1_data.mac_addr, art + DR344_MAC1_OFFSET, 0);
> +
> + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
> + AR934X_ETH_CFG_SW_ONLY_MODE);
> +
> + /* GMAC0 is connected to an AR8327 switch */
> + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
> + ath79_eth0_data.phy_mask = BIT(0);
> + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
> + ath79_eth0_pll_data.pll_1000 = 0x06000000;
> +
> + /* GMAC1 is connected to the internal switch */
> + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
> + ath79_eth1_data.speed = SPEED_1000;
> + ath79_eth1_data.duplex = DUPLEX_FULL;
> +
> + ath79_register_eth(0);
> + ath79_register_eth(1);
> +}
> +
> +MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344",
> dr344_setup); diff -Nru
> a/target/linux/ar71xx/generic/profiles/wallys.mk
> b/target/linux/ar71xx/generic/profiles/wallys.mk
> --- a/target/linux/ar71xx/generic/profiles/wallys.mk 1970-01-01
> 01:00:00.000000000 +0100
> +++ b/target/linux/ar71xx/generic/profiles/wallys.mk 2015-10-27
> 11:27:41.139057668 +0100
> @@ -0,0 +1,17 @@
> +#
> +# Copyright (C) 2015 Philippe DUCHEIN <pduch...@gmail.com>
> +# Copyright (C) 2009 OpenWrt.org
> +# This is free software, licensed under the GNU General Public License v2.
> +# See /LICENSE for more information.
> +#
> +
> +define Profile/DR344
> + NAME:=Wallys DR344
> +endef
> +
> +define Profile/DR344/Description
> + Package set optimized for the Wallys DR344 board.
> +endef
> +
> +$(eval $(call Profile,DR344))
> +
> diff -Nru a/target/linux/ar71xx/image/Makefile
> b/target/linux/ar71xx/image/Makefile
> --- a/target/linux/ar71xx/image/Makefile 2015-10-27 11:22:06.230108013
> +0100
> +++ b/target/linux/ar71xx/image/Makefile 2015-10-27 11:27:41.139057668
> +0100
> @@ -1457,6 +1457,7 @@
>
> whrhpg300n_mtdlayout=mtdparts=spi0.0:248k(u-boot)ro,8k(u-boot-env)ro,3712k(firmware),64k(art)ro
>
> wlr8100_mtdlayout=mtdparts=spi0.0:192k(u-boot)ro,64k(u-boot-env)ro,1408k(kernel),14080k(rootfs),192k(unknown)ro,64k(art)ro,384k(unknown2)ro,15488k@0x40000(firmware)
>
> wpj344_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro
> +dr344_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,6336k(rootfs),1408k(kernel),64k(nvram),64k(art)ro,7744k@0x50000(firmware)
>
> wpj531_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro
>
> wpj558_mtdlayout_16M=mtdparts=spi0.0:192k(u-boot)ro,16128k(firmware),64k(art)ro
>
> wndap360_mtdlayout=mtdparts=spi0.0:256k(u-boot)ro,64k(u-boot-env)ro,1728k(kernel),6016k(rootfs),64k(nvram)ro,64k(art)ro,7744k@0x50000(firmware)
> @@ -2293,6 +2294,7 @@
> $(eval $(call
> SingleProfile,AthLzma,64k,TUBE2H16M,tube2h-16M,TUBE2H,ttyATH0,115200,$$(alfa_mtdlayout_16M),KRuImage,65536))
> $(eval $(call
> SingleProfile,AthLzma,64k,WLR8100,wlr8100,WLR8100,ttyS0,115200,$$(wlr8100_mtdlayout),KRuImage))
> $(eval $(call
> SingleProfile,AthLzma,64k,WPJ344_16M,wpj344-16M,WPJ344,ttyS0,115200,$$(wpj344_mtdlayout_16M),KRuImage,65536))
> +$(eval $(call
> SingleProfile,AthLzma,64k,DR344,dr344,DR344,ttyS0,115200,$$(dr344_mtdlayout),RKuImage))
> $(eval $(call
> SingleProfile,AthLzma,64k,WPJ531_16M,wpj531-16M,WPJ531,ttyS0,115200,$$(wpj531_mtdlayout_16M),KRuImage,65536))
> $(eval $(call
> SingleProfile,AthLzma,64k,WPJ558_16M,wpj558-16M,WPJ558,ttyS0,115200,$$(wpj558_mtdlayout_16M),KRuImage,65536))
>
> @@ -2424,6 +2426,7 @@
> $(eval $(call MultiProfile,WP543,WP543_2M WP543_4M WP543_8M WP543_16M))
> $(eval $(call MultiProfile,WPE72,WPE72_4M WPE72_8M WPE72_16M))
> $(eval $(call MultiProfile,WPJ344,WPJ344_16M))
> +
> $(eval $(call MultiProfile,WPJ531,WPJ531_16M))
> $(eval $(call MultiProfile,WPJ558,WPJ558_16M))
>
> diff -Nru
> a/target/linux/ar71xx/patches-4.1/701-MIPS-ath79-openwrt-dr344.patch
> b/target/linux/ar71xx/patches-4.1/701-MIPS-ath79-openwrt-dr344.patch
> --- a/target/linux/ar71xx/patches-4.1/701-MIPS-ath79-openwrt-dr344.patch
> 1970-01-01 01:00:00.000000000 +0100
> +++ b/target/linux/ar71xx/patches-4.1/701-MIPS-ath79-openwrt-dr344.patch
> 2015-10-27 11:44:47.189134768 +0100
> @@ -0,0 +1,295 @@
> +--- a/arch/mips/ath79/machtypes.h 2015-09-07 12:39:52.070426175 +0200
> ++++ b/arch/mips/ath79/machtypes.h 2015-09-07 12:41:03.181395126 +0200
> +@@ -220,6 +220,7 @@
> + ATH79_MACH_WZR_450HP2, /* Buffalo WZR-450HP2 */
> + ATH79_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */
> + ATH79_MACH_ZCN_1523H_5, /* Zcomax ZCN-1523H-5-xx */
> ++ ATH79_MACH_DR344, /* Wallys DR344 */
This is sorted too...
> + };
> +
> + #endif /* _ATH79_MACHTYPE_H */
> +--- a/arch/mips/ath79/Kconfig 2015-09-07 12:47:19.239505173 +0200
> ++++ b/arch/mips/ath79/Kconfig 2015-09-07 12:48:35.322536257 +0200
> +@@ -371,6 +371,16 @@
> + select ATH79_DEV_USB
> + select ATH79_DEV_WMAC
> +
> ++config ATH79_MACH_DR344
> ++ bool "Wallys DR344 board support"
> ++ select SOC_AS934X
> ++ select ATH79_DEV_ETH
> ++ select ATH79_DEV_GPIO_BUTTONS
> ++ select ATH79_DEV_LEDS_GPIO
> ++ select ATH79_DEV_M25P80
> ++ select ATH79_DEV_USB
> ++ select ATH79_DEV_WMAC
> ++
> + config ATH79_MACH_WPJ531
> + bool "Compex WPJ531 board support"
> + select SOC_QCA953X
> +--- a/arch/mips/ath79/Makefile 2015-09-07 12:43:35.519467968 +0200
> ++++ b/arch/mips/ath79/Makefile 2015-09-07 12:44:15.198007230 +0200
> +@@ -171,3 +171,4 @@
> + obj-$(CONFIG_ATH79_MACH_ZCN_1523H) += mach-zcn-1523h.o
> + obj-$(CONFIG_ATH79_MACH_CARAMBOLA2) += mach-carambola2.o
> + obj-$(CONFIG_ATH79_MACH_NBG6716) += mach-nbg6716.o
> ++obj-$(CONFIG_ATH79_MACH_DR344) += mach-dr344.o
> +diff -Nru a/arch/mips/ath79/mach-dr344.c
> b/arch/mips/ath79/mach-dr344.c
> +--- a/arch/mips/ath79/mach-dr344.c 2015-09-18 04:40:26.332357634 -0700
> ++++ b/arch/mips/ath79/mach-dr344.c 2015-09-18 23:47:29.312975398 -0700
> +@@ -25,7 +25,7 @@
> + #include <linux/ar8216_platform.h>
> +
> + #include <asm/mach-ath79/ar71xx_regs.h>
> +-
> ++#include <linux/platform_data/phy-at803x.h>
> + #include "common.h"
> + #include "pci.h"
> + #include "dev-ap9x-pci.h"
> +@@ -92,43 +92,18 @@
> + .active_low = 1,
> + },
> + };
> +-
> +-static struct ar8327_pad_cfg dr344_ar8327_pad0_cfg = {
> +- .mode = AR8327_PAD_MAC_RGMII,
> +- .txclk_delay_en = true,
> +- .rxclk_delay_en = true,
> +- .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
> +- .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
> +-};
> +-
> +-static struct ar8327_led_cfg dr344_ar8327_led_cfg = {
> +- .led_ctrl0 = 0x00000000,
> +- .led_ctrl1 = 0xc737c737,
> +- .led_ctrl2 = 0x00000000,
> +- .led_ctrl3 = 0x00c30c00,
> +- .open_drain = true,
> +-};
> +-
> +-static struct ar8327_platform_data dr344_ar8327_data = {
> +- .pad0_cfg = &dr344_ar8327_pad0_cfg,
> +- .port0_cfg = {
> +- .force_link = 1,
> +- .speed = AR8327_PORT_SPEED_1000,
> +- .duplex = 1,
> +- .txpause = 1,
> +- .rxpause = 1,
> +- },
> +- .led_cfg = &dr344_ar8327_led_cfg,
> +-};
> +-
> +-static struct mdio_board_info dr344_mdio0_info[] = {
> +- {
> +- .bus_id = "ag71xx-mdio.0",
> +- .phy_addr = 0,
> +- .platform_data = &dr344_ar8327_data,
> +- },
> +-};
> +-
> ++ static struct at803x_platform_data dr344_ar8035_data = {
> ++ .enable_rgmii_tx_delay = 1,
> ++ .enable_rgmii_rx_delay = 1,
> ++ };
> ++
> ++ static struct mdio_board_info dr344_mdio0_info[] = {
> ++ {
> ++ .bus_id = "ag71xx-mdio.0",
> ++ .phy_addr = 0,
> ++ .platform_data = &dr344_ar8035_data,
> ++ },
> ++ };
> + static void __init dr344_setup(void)
> + {
> + u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
> +@@ -151,9 +126,9 @@
> +
> + ath79_register_mdio(1, 0x0);
> + ath79_register_mdio(0, 0x0);
> +-
> +- ath79_init_mac(ath79_eth0_data.mac_addr, art + DR344_MAC0_OFFSET, 0);
> +- ath79_init_mac(ath79_eth1_data.mac_addr, art + DR344_MAC1_OFFSET, 0);
> ++
> ++ ath79_init_mac(ath79_eth0_data.mac_addr, (u8 *)0xbf03f810, 0);
> ++ ath79_init_mac(ath79_eth1_data.mac_addr, (u8 *)0xbf03f818, 0);
> +
> + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
> + AR934X_ETH_CFG_SW_ONLY_MODE);
> +@@ -162,8 +137,10 @@
> + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
> + ath79_eth0_data.phy_mask = BIT(0);
> + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
> +- ath79_eth0_pll_data.pll_1000 = 0x06000000;
> +-
> ++ ath79_eth0_pll_data.pll_1000 = 0x0e000000;
> ++ ath79_eth0_pll_data.pll_100 = 0x0101;
> ++ ath79_eth0_pll_data.pll_10 = 0x1313;
> ++
> + /* GMAC1 is connected to the internal switch */
> + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
> + ath79_eth1_data.speed = SPEED_1000;
> +
> +
> +
This is patching your own file you added? Why not just put the
right file in from the beginning?
> +diff -Nru linux-4.1.11.org/drivers/net/phy/atheros.c
> linux-4.1.11/drivers/net/phy/atheros.c
> +--- linux-4.1.11.org/drivers/net/phy/atheros.c 1969-12-31
> 16:00:00.000000000 -0800
> ++++ linux-4.1.11/drivers/net/phy/atheros.c 2015-09-18 23:48:18.972973326
> -0700
> +@@ -0,0 +1,133 @@
> ++/*
> ++ * Driver for Atheros PHYs
> ++ *
> ++ *
> ++ * This program is free software; you can redistribute it and/or modify it
> ++ * under the terms of the GNU General Public License version 2 as published
> ++ * by the Free Software Foundation.
> ++ *
> ++ */
> ++
> ++#include <linux/module.h>
> ++#include <linux/delay.h>
> ++#include <linux/skbuff.h>
> ++#include <linux/phy.h>
> ++#include <asm/mach-ath79/ath79.h>
> ++
> ++/* Phy Specific status fields */
> ++#define ATHER_STATUS_LINK_MASK 0xC000 ++#define
> ATHER_STATUS_LINK_SHIFT 14 ++#define ATHER_STATUS_FULL_DUPLEX
> 0x2000 ++#define ATHR_STATUS_LINK_PASS 0x0400 ++#define
> ATHR_STATUS_RESOVLED 0x0800
> ++
> ++#define ATHR_PHY_SPEC_STATUS 17
> ++#define ATHR_DEBUG_PORT_ADDRESS 29
> ++#define ATHR_DEBUG_PORT_DATA 30
> ++
> ++static u16 debug0 = 0x14e;
> ++static u16 debug5 = 0x147;
> ++static u16 debug5_1000 = 0x0;
> ++
> ++static int ar8035_config_init(struct phy_device *phydev)
> ++{
> ++ phy_write(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
> ++ return 0;
> ++}
> ++
> ++static int ar8035_read_status(struct phy_device *phydev)
> ++{
> ++ int status;
> ++
> ++ status = phy_read(phydev, ATHR_PHY_SPEC_STATUS);
> ++ if (status < 0)
> ++ return status;
> ++
> ++ if ((status & ATHR_STATUS_LINK_PASS) && (status &
> ATHR_STATUS_RESOVLED)) {
> ++ phydev->link = 1;
> ++ } else {
> ++ phydev->link = 0;
> ++ }
> ++
> ++ if ( phydev->link ) {
> ++ if (status & ATHER_STATUS_FULL_DUPLEX)
> ++ phydev->duplex = DUPLEX_FULL;
> ++ else
> ++ phydev->duplex = DUPLEX_HALF;
> ++
> ++ status = ((status & ATHER_STATUS_LINK_MASK) >>
> ATHER_STATUS_LINK_SHIFT);
> ++ switch(status) {
> ++ case 0:
> ++ if ( phydev->speed != SPEED_10 ) {
> ++ phy_write(phydev, ATHR_DEBUG_PORT_ADDRESS, 0x0);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_DATA, debug0);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_ADDRESS, 0x5);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_DATA, debug5);
> ++ phydev->speed = SPEED_10;
> ++ }
> ++ break;
> ++ case 1:
> ++ if ( phydev->speed != SPEED_100 ) {
> ++ phy_write(phydev, ATHR_DEBUG_PORT_ADDRESS, 0x0);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_DATA, debug0);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_ADDRESS, 0x5);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_DATA, debug5);
> ++ phydev->speed = SPEED_100;
> ++ }
> ++ break;
> ++ case 2:
> ++ if ( phydev->speed != SPEED_1000 ) {
> ++ phy_write(phydev, ATHR_DEBUG_PORT_ADDRESS, 0x0);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_DATA, debug0);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_ADDRESS, 0x5);
> ++ phy_write(phydev, ATHR_DEBUG_PORT_DATA,
> debug5_1000);
> ++ phydev->speed = SPEED_1000;
> ++ }
> ++ break;
> ++ }
> ++ }
> ++
> ++ return 0;
> ++}
> ++
> ++
> ++static struct phy_driver ar8035_phy_driver = {
> ++ .phy_id = 0x004dd072,
> ++ .name = "Atheros AR8035",
> ++ .phy_id_mask = 0xffffffff,
> ++ .features = PHY_GBIT_FEATURES,
> ++ .config_init = ar8035_config_init,
> ++ .config_aneg = genphy_config_aneg,
> ++ .read_status = ar8035_read_status,
> ++ .driver = {
> ++ .owner = THIS_MODULE,
> ++ },
> ++};
> ++
> ++static int __init atheros_phy_init(void)
> ++{
> ++ if ( ath79_soc == ATH79_SOC_AR7130 ||
> ++ ath79_soc == ATH79_SOC_AR7141 ||
> ++ ath79_soc == ATH79_SOC_AR7161 ) {
> ++ debug0 = 0x82EE;
> ++ debug5 = 0x2D47;
> ++ debug5_1000 = 0x2D47;
> ++ }
> ++ return phy_driver_register(&ar8035_phy_driver);
> ++}
> ++
> ++static void __exit atheros_phy_exit(void)
> ++{
> ++ phy_driver_unregister(&ar8035_phy_driver);
> ++}
> ++
> ++#ifdef MODULE
> ++module_init(atheros_phy_init);
> ++module_exit(atheros_phy_exit);
> ++#else
> ++subsys_initcall(atheros_phy_init);
> ++#endif
> ++
> ++MODULE_DESCRIPTION("Atheros PHY driver");
> ++MODULE_LICENSE("GPL v2");
> ++
> +diff -Nru linux-4.1.11.org/drivers/net/phy/Kconfig
> linux-4.1.11/drivers/net/phy/Kconfig
> +--- linux-4.1.11.org/drivers/net/phy/Kconfig 2015-09-18 23:45:39.496979979
> -0700
> ++++ linux-4.1.11/drivers/net/phy/Kconfig 2015-09-18 23:48:18.972973326
> -0700
> +@@ -133,6 +133,10 @@
> + ---help---
> + Supports the KSZ9021, VSC8201, KS8001 PHYs.
> +
> ++config ATHEROS_PHY
> ++ tristate "Driver for Atheros PHYs"
> ++ ---help---
> ++ Supports the AR8035 PHY.
> + config ADM6996_PHY
> + tristate "Driver for ADM6996 switches"
> + select SWCONFIG
> +diff -Nru linux-4.1.11.org/drivers/net/phy/Makefile
> linux-4.1.11/drivers/net/phy/Makefile
> +--- linux-4.1.11.org/drivers/net/phy/Makefile 2015-09-18
> 23:45:39.496979979 -0700
> ++++ linux-4.1.11/drivers/net/phy/Makefile 2015-09-18 23:48:18.952973327
> -0700
> +@@ -31,6 +31,7 @@
> + obj-$(CONFIG_RTL8367_PHY) += rtl8367.o
> + obj-$(CONFIG_RTL8367B_PHY) += rtl8367b.o
> + obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
> ++obj-$(CONFIG_ATHEROS_PHY) += atheros.o
> + obj-$(CONFIG_PSB6970_PHY) += psb6970.o
> + obj-$(CONFIG_B53) += b53/
> + obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
> _______________________________________________
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> openwrt-devel@lists.openwrt.org
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