This adds the Vitesse G5e ethernet switch to the Square One Itian SQ201 router device tree.
Signed-off-by: Linus Walleij <linus.wall...@linaro.org>
---
arch/arm/boot/dts/gemini-sq201.dts | 75 +++++++++++++++++++++++++++++-
1 file changed, 73 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/gemini-sq201.dts
b/arch/arm/boot/dts/gemini-sq201.dts
index 2706b86e06f1..830c167012a0 100644
--- a/arch/arm/boot/dts/gemini-sq201.dts
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200n8";
+ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = &uart0;
};
@@ -70,6 +70,61 @@
};
};
+ spi {
+ compatible = "spi-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Check pin collisions */
+ gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+ num-chipselects = <1>;
+
+ switch@0 {
+ compatible = "vitesse,vsc7395";
+ reg = <0>;
+ /* Specified for 2.5 MHz or below */
+ spi-max-frequency = <2500000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+ vsc: port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac1>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+
+
soc {
flash@30000000 {
/*
@@ -135,6 +190,16 @@
"gpio0kgrp";
};
};
+ /*
+ * gpio0dgrp cover lines used by the SPI
+ * to the Vitesse G5x chip.
+ */
+ gpio1_default_pins: pinctrl-gpio1 {
+ mux {
+ function = "gpio1";
+ groups = "gpio1dgrp";
+ };
+ };
pinctrl-gmii {
mux {
function = "gmii";
@@ -205,6 +270,11 @@
pinctrl-0 = <&gpio0_default_pins>;
};
+ gpio1: gpio@4e000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio1_default_pins>;
+ };
+
pci@50000000 {
status = "okay";
interrupt-map-mask = <0xf800 0 0 7>;
@@ -235,7 +305,8 @@
phy-handle = <&phy0>;
};
ethernet-port@1 {
- /* Used for the Vitesse G5 chip, add later */
+ phy-mode = "rgmii";
+ phy-handle = <&vsc>;
};
};
--
2.17.1
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