Add a switch reset on brcm63xx SoCs to ensure a sane state before initializiating the switch.
Performing this reset on BCM6368 solves the ticket #1925 on the Observa VH4032N: - brcm63xx: VH4032N: no traffic between b53 lan switch ports. Other devices with different SoCs may be also affected but they wasn't still tested, so don't perform the reset on them for now. Furthermore some bcm63xx SoCs doesn't have registers to perform the reset (i.e BCM6358, BCM6348). Signed-off-by: Daniel Gonzalez Cabanelas <[email protected]> --- .../425-bcm63xx_enet_add_switch_soft_reset.patch | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 target/linux/brcm63xx/patches-4.14/425-bcm63xx_enet_add_switch_soft_reset.patch diff --git a/target/linux/brcm63xx/patches-4.14/425-bcm63xx_enet_add_switch_soft_reset.patch b/target/linux/brcm63xx/patches-4.14/425-bcm63xx_enet_add_switch_soft_reset.patch new file mode 100644 index 0000000..2726593 --- /dev/null +++ b/target/linux/brcm63xx/patches-4.14/425-bcm63xx_enet_add_switch_soft_reset.patch @@ -0,0 +1,64 @@ +--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c ++++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c +@@ -2691,6 +2691,48 @@ static const struct ethtool_ops bcm_enet + .set_ringparam = bcm_enetsw_set_ringparam, + }; + ++static void bcm_enetsw_soft_reset(void) ++{ ++ u32 reg, mask, offs; ++ ++ if (BCMCPU_IS_6318()) { ++ offs = PERF_SOFTRESET_6318_REG; ++ mask = SOFTRESET_6318_ENETSW_MASK; ++ } ++ else if (BCMCPU_IS_6328()) { ++ offs = PERF_SOFTRESET_6328_REG; ++ mask = SOFTRESET_6328_ENETSW_MASK; ++ } ++ else if (BCMCPU_IS_6358()) { ++ offs = PERF_SOFTRESET_6358_REG; ++ mask = 0; ++ } ++ else if (BCMCPU_IS_6362()) { ++ offs = PERF_SOFTRESET_6362_REG; ++ mask = SOFTRESET_6362_ENETSW_MASK; ++ } ++ else if (BCMCPU_IS_6368()) { ++ offs = PERF_SOFTRESET_6368_REG; ++ mask = SOFTRESET_6368_ENETSW_MASK; ++ } ++ else if (BCMCPU_IS_63268()) { ++ offs = PERF_SOFTRESET_63268_REG; ++ mask = SOFTRESET_63268_ENETSW_MASK; ++ } ++ else { ++ offs = PERF_SOFTRESET_REG; ++ mask = 0; ++ } ++ ++ reg = bcm_perf_readl(offs); ++ reg &= ~mask; ++ bcm_perf_writel(reg, offs); ++ udelay(1000); ++ reg |= mask; ++ bcm_perf_writel(reg, offs); ++ udelay(1000); ++} ++ + /* allocate netdevice, request register memory and register device. */ + static int bcm_enetsw_probe(struct platform_device *pdev) + { +@@ -2784,6 +2826,12 @@ static int bcm_enetsw_probe(struct platf + priv->pdev = pdev; + priv->net_dev = dev; + ++ /* Reset the switch to ensure a sane state on the required SoCs. ++ * Only tested on 6368. More SoCs may also need this ++ */ ++ if (BCMCPU_IS_6368()) ++ bcm_enetsw_soft_reset(); ++ + /* reset mib */ + val = enetsw_readb(priv, ENETSW_GMCR_REG); + val |= ENETSW_GMCR_RST_MIB_MASK; -- 2.6.4 _______________________________________________ openwrt-devel mailing list [email protected] https://lists.openwrt.org/mailman/listinfo/openwrt-devel
