TODO: the spi-mt7621 patches will break support for other targets Signed-off-by: Rafaël Carré <fun...@videolan.org> --- ...-ralink-adds-support-for-RT6855A-SoC.patch | 688 ++++++ .../304-HACK-spi-mt7621-rt6855a-fix.patch | 35 + ...HACK-spi-mt7621.c-hardcode-frequency.patch | 69 + .../306-RT6855A-add-watchdog.patch | 236 +++ ...855A-Use-Linksys-provided-PCI-driver.patch | 1884 +++++++++++++++++ 5 files changed, 2912 insertions(+) create mode 100644 target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch create mode 100644 target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch create mode 100644 target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch create mode 100644 target/linux/ramips/patches-5.4/306-RT6855A-add-watchdog.patch create mode 100644 target/linux/ramips/patches-5.4/307-HACK-RT6855A-Use-Linksys-provided-PCI-driver.patch
diff --git a/target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch b/target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch new file mode 100644 index 0000000000..dc56e6c209 --- /dev/null +++ b/target/linux/ramips/patches-5.4/303-MIPS-ralink-adds-support-for-RT6855A-SoC.patch @@ -0,0 +1,688 @@ +From 7d3e6a27ac47b16d7b0b05d4ce186c48cc054625 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org> +Date: Wed, 23 Dec 2020 14:16:37 +0100 +Subject: [PATCH 1/5] MIPS: ralink: adds support for RT6855A SoC +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +TODO: +- clean up dts file + some things are OpenWrt-only (mtd mac / eeprom) + some things might be removed (gdma?) + spi / pci should be moved to other commits + ethernet should go in OpenWrt dts + +All code is my own or based on existing in-tree files. + +Signed-off-by: Rafaël Carré <fun...@videolan.org> +--- + arch/mips/boot/dts/ralink/Makefile | 1 + + arch/mips/boot/dts/ralink/rt6855.dtsi | 207 ++++++++++++++++++ + arch/mips/boot/dts/ralink/wap300n.dts | 22 ++ + .../include/asm/mach-ralink/ralink_regs.h | 1 + + arch/mips/ralink/Kconfig | 13 +- + arch/mips/ralink/Makefile | 6 +- + arch/mips/ralink/Platform | 5 + + arch/mips/ralink/early_printk.c | 5 +- + arch/mips/ralink/irq-rt6855a.c | 172 +++++++++++++++ + arch/mips/ralink/reset.c | 23 ++ + arch/mips/ralink/rt6855a.c | 57 +++++ + 11 files changed, 509 insertions(+), 3 deletions(-) + create mode 100644 arch/mips/boot/dts/ralink/rt6855.dtsi + create mode 100644 arch/mips/boot/dts/ralink/wap300n.dts + create mode 100644 arch/mips/ralink/irq-rt6855a.c + create mode 100644 arch/mips/ralink/rt6855a.c + +diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile +index 6c26dfa0a903..08c612190936 100644 +--- a/arch/mips/boot/dts/ralink/Makefile ++++ b/arch/mips/boot/dts/ralink/Makefile +@@ -3,6 +3,7 @@ dtb-$(CONFIG_DTB_RT2880_EVAL) += rt2880_eval.dtb + dtb-$(CONFIG_DTB_RT305X_EVAL) += rt3052_eval.dtb + dtb-$(CONFIG_DTB_RT3883_EVAL) += rt3883_eval.dtb + dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb ++dtb-$(CONFIG_DTB_WAP300N) += wap300n.dtb + dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb + dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb + +diff --git a/arch/mips/boot/dts/ralink/rt6855.dtsi b/arch/mips/boot/dts/ralink/rt6855.dtsi +new file mode 100644 +index 000000000000..8427696ff7bf +--- /dev/null ++++ b/arch/mips/boot/dts/ralink/rt6855.dtsi +@@ -0,0 +1,207 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "ralink,rt6855a-soc"; ++ ++ cpus { ++ cpu@0 { ++ compatible = "mips,mips34Kc"; ++ }; ++ }; ++ ++ cpuintc: cpuintc { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ compatible = "mti,cpu-interrupt-controller"; ++ }; ++ ++ palmbus@1fb00000 { ++ compatible = "palmbus"; ++ reg = <0x1fb00000 0xe0000>; ++ ranges = <0x0 0x1fb00000 0x100000>; ++ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ sysc@0 { ++ compatible = "ralink,rt6855a-sysc"; ++ reg = <0x0 0x100>; ++ }; ++ ++ intc: intc@40000 { ++ compatible = "ralink,rt6855a-intc"; ++ reg = <0x40000 0x100>; ++ ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ interrupt-parent = <&cpuintc>; ++ }; ++ ++ memc@300 { ++ compatible = "ralink,rt6855a-memc", "ralink,rt3050-memc"; ++ reg = <0x300 0x100>; ++ }; ++ ++ watchdog@f0100 { ++ compatible = "ralink,rt6855a-wdt"; ++ reg = <0xf0100 0x10>; ++ }; ++ ++ uart: uart@f0000 { ++ compatible = "ns8250"; ++ reg = <0xf0000 0x30>; ++ interrupts = <0>; ++ ++ clock-frequency = <921600>; ++ ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ no-loopback-test; ++ ++ status = "okay"; ++ ++ interrupt-parent = <&intc>; ++ }; ++ ++ gdma: gdma@30000 { ++ compatible = "ralink,gdma-rt2880"; ++ reg = <0x30000 0x100>; ++ }; ++ ++ ethernet: ethernet@50000{ ++ compatible = "ralink,rt6855a-eth"; ++ reg = <0x50000 0x10000>; ++ ++ interrupt-parent = <&intc>; ++ interrupts = <21>; ++ ++ mediatek,switch = <&esw>; ++ mtd-mac-address = <&factory 0xe000>; ++ }; ++ ++ esw: esw@60000 { ++ compatible = "ralink,rt3050-esw"; ++ reg = <0x60000 0x8000>; ++ ++ interrupt-parent = <&intc>; ++ interrupts = <15>; ++ }; ++ ++ spi0: spi@c0b00 { ++ status = "disabled"; ++ ++ compatible = "ralink,mt7621-spi"; ++ reg = <0xc0b00 0x100>; ++ ++ //clocks = <&pll MT7621_CLK_BUS>; ++ ++ //resets = <&rstctrl 18>; ++ //reset-names = "spi"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ //pinctrl-names = "default"; ++ //pinctrl-0 = <&spi_pins>; ++ }; ++ }; ++ ++ pci: pci@1fb80000 { ++ compatible = "ralink,rt3883-pci"; ++ reg = <0x1fb80000 0x20000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; /* direct mapping */ ++ ++ status = "disabled"; ++ ++ pciintc: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ ++ interrupt-parent = <&cpuintc>; ++ interrupts = <4>; ++ }; ++ ++ pci@0 { ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ++ device_type = "pci"; ++ ++ bus-range = <0 1>; ++ ranges = < ++ 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ ++ 0x01000000 0 0x00000000 0x1f600000 0 0x00010000 /* io space */ ++ >; ++ ++ pci0: pci@0 { ++ reg = <0x2000 0 0 0 0>; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ status = "okay"; ++ ++ bus-range = <0 1>; ++ ranges; ++ }; ++ }; ++ }; ++ ++}; ++ ++&spi0 { ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "Bootloader"; ++ reg = <0x0 0x30000>; ++ read-only; ++ }; ++ ++ partition@30000 { ++ label = "Config"; ++ reg = <0x30000 0x10000>; ++ read-only; ++ }; ++ ++ factory: partition@40000 { ++ label = "Factory"; ++ reg = <0x40000 0x10000>; ++ read-only; ++ }; ++ ++ partition@50000 { ++ compatible = "denx,uimage"; ++ label = "Kernel"; ++ reg = <0x50000 0x7b0000>; ++ }; ++ }; ++ }; ++}; ++ ++&pci0 { ++ wifi@0,0 { ++ compatible = "pci1814,3091"; ++ reg = <0x0000 0 0 0 0>; ++ ralink,2ghz = <0>; ++ ralink,mtd-eeprom = <&factory 0x8000>; ++ }; ++}; ++ +diff --git a/arch/mips/boot/dts/ralink/wap300n.dts b/arch/mips/boot/dts/ralink/wap300n.dts +new file mode 100644 +index 000000000000..e8f81578a589 +--- /dev/null ++++ b/arch/mips/boot/dts/ralink/wap300n.dts +@@ -0,0 +1,22 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/dts-v1/; ++ ++/include/ "rt6855.dtsi" ++ ++/ { ++ compatible = "ralink,rt6855a-soc"; ++ model = "Linksys WAP300n"; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x20000 0x3fe0000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,57600"; ++ }; ++ ++ pci@1fb80000 { ++ status = "okay"; ++ }; ++}; +diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h +index 9dbd9f0870c9..0e947616fa43 100644 +--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h ++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h +@@ -26,6 +26,7 @@ enum ralink_soc_type { + MT762X_SOC_MT7621AT, + MT762X_SOC_MT7628AN, + MT762X_SOC_MT7688, ++ RT6855A_SOC, + }; + extern enum ralink_soc_type ralink_soc; + +diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig +index 1434fa60f3db..312a8efee306 100644 +--- a/arch/mips/ralink/Kconfig ++++ b/arch/mips/ralink/Kconfig +@@ -16,7 +16,7 @@ config RALINK_ILL_ACC + config IRQ_INTC + bool + default y +- depends on !SOC_MT7621 ++ depends on !SOC_MT7621 && !SOC_RT6855A + + choice + prompt "Ralink SoC selection" +@@ -36,6 +36,12 @@ choice + bool "RT3883" + select HAVE_PCI + ++ config SOC_RT6855A ++ bool "RT6855A" ++ select HAVE_LEGACY_CLK ++ select HAVE_PCI ++ select MII ++ + config SOC_MT7620 + bool "MT7620/8" + select CPU_MIPSR2_IRQ_VI +@@ -92,6 +98,11 @@ choice + depends on SOC_MT7620 + select BUILTIN_DTB + ++ config DTB_WAP300N ++ bool "WAP300N" ++ depends on SOC_RT6855A ++ select BUILTIN_DTB ++ + endchoice + + endif +diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile +index 26fabbdea1f1..2bb8ddd69dff 100644 +--- a/arch/mips/ralink/Makefile ++++ b/arch/mips/ralink/Makefile +@@ -7,7 +7,10 @@ + obj-y := prom.o of.o reset.o + + ifndef CONFIG_MIPS_GIC +- obj-y += clk.o timer.o ++obj-y += clk.o ++ifndef CONFIG_SOC_RT6855A ++ obj-y += timer.o ++endif + endif + + obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o +@@ -22,6 +25,7 @@ obj-$(CONFIG_SOC_RT305X) += rt305x.o + obj-$(CONFIG_SOC_RT3883) += rt3883.o + obj-$(CONFIG_SOC_MT7620) += mt7620.o + obj-$(CONFIG_SOC_MT7621) += mt7621.o ++obj-$(CONFIG_SOC_RT6855A) += rt6855a.o irq-rt6855a.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform +index 6095fcc334f4..143b88c5694b 100644 +--- a/arch/mips/ralink/Platform ++++ b/arch/mips/ralink/Platform +@@ -22,6 +22,11 @@ cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt + load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000 + cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883 + ++# Ralink RT6855A ++# ++load-$(CONFIG_SOC_RT6855A) += 0xffffffff80020000 ++cflags-$(CONFIG_SOC_RT6855A) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) ++ + # + # Ralink MT7620 + # +diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c +index eb4fac25eaf6..7aff0b8d5b82 100644 +--- a/arch/mips/ralink/early_printk.c ++++ b/arch/mips/ralink/early_printk.c +@@ -16,6 +16,9 @@ + #elif defined(CONFIG_SOC_MT7621) + #define EARLY_UART_BASE 0x1E000c00 + #define CHIPID_BASE 0x1E000004 ++#elif defined(CONFIG_SOC_RT6855A) ++#define EARLY_UART_BASE 0x1FBF0000 ++#define CHIPID_BASE 0x1E000004 + #else + #define EARLY_UART_BASE 0x10000c00 + #define CHIPID_BASE 0x10000004 +@@ -74,7 +77,7 @@ void prom_putchar(char ch) + init_complete = 1; + } + +- if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) { ++ if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628() || IS_ENABLED(CONFIG_SOC_RT6855A)) { + uart_w32((unsigned char)ch, UART_TX); + while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) + ; +diff --git a/arch/mips/ralink/irq-rt6855a.c b/arch/mips/ralink/irq-rt6855a.c +new file mode 100644 +index 000000000000..9f04d8af7037 +--- /dev/null ++++ b/arch/mips/ralink/irq-rt6855a.c +@@ -0,0 +1,172 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * ++ * Copyright (C) 2009 Gabor Juhos <juh...@openwrt.org> ++ * Copyright (C) 2013 John Crispin <j...@phrozen.org> ++ * Copyright (C) 2020 Rafaël Carré <fun...@videolan.org> ++ */ ++ ++#include <linux/io.h> ++#include <linux/bitops.h> ++#include <linux/of_platform.h> ++#include <linux/of_address.h> ++#include <linux/of_irq.h> ++#include <linux/irqdomain.h> ++#include <linux/interrupt.h> ++ ++#include <asm/irq_cpu.h> ++#include <ioremap.h> ++#include <asm/mipsregs.h> ++ ++#include "common.h" ++ ++/* we have a cascade of 8 irqs */ ++#define RALINK_INTC_IRQ_BASE 8 ++ ++/* we have 32 SoC irqs */ ++#define RALINK_INTC_IRQ_COUNT 32 ++ ++#define RALINK_SOC_IRQ_TIMER 30 ++ ++enum rt_intc_regs_enum { ++ INTC_REG_MASK = 0, ++ INTC_REG_PRIO, ++}; ++ ++static u32 rt_intc_regs[] = { ++ [INTC_REG_MASK] = 0x04, ++ [INTC_REG_PRIO] = 0x10, ++}; ++ ++static DEFINE_SPINLOCK(rt6855_irq_lock); ++ ++static void __iomem *rt_intc_membase; ++ ++static inline void rt_intc_w32(u32 val, unsigned reg) ++{ ++ __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]); ++} ++ ++static inline void rt_intc_prio_w8(u32 val, unsigned prio) ++{ ++ __raw_writeb(val, rt_intc_membase + rt_intc_regs[INTC_REG_PRIO] + prio); ++} ++ ++static inline u32 rt_intc_r32(unsigned reg) ++{ ++ return __raw_readl(rt_intc_membase + rt_intc_regs[reg]); ++} ++ ++static void ralink_intc_irq_unmask(struct irq_data *d) ++{ ++ unsigned long flags; ++ u32 mask; ++ ++ spin_lock_irqsave(&rt6855_irq_lock, flags); ++ ++ mask = rt_intc_r32(INTC_REG_MASK); ++ mask |= BIT(d->hwirq); ++ rt_intc_w32(mask, INTC_REG_MASK); ++ ++ spin_unlock_irqrestore(&rt6855_irq_lock, flags); ++} ++ ++static void ralink_intc_irq_mask(struct irq_data *d) ++{ ++ unsigned long flags; ++ u32 mask; ++ ++ spin_lock_irqsave(&rt6855_irq_lock, flags); ++ ++ mask = rt_intc_r32(INTC_REG_MASK); ++ mask &= ~BIT(d->hwirq); ++ rt_intc_w32(mask, INTC_REG_MASK); ++ ++ spin_unlock_irqrestore(&rt6855_irq_lock, flags); ++} ++ ++static struct irq_chip ralink_intc_irq_chip = { ++ .name = "INTC", ++ .irq_ack = ralink_intc_irq_mask, ++ .irq_mask = ralink_intc_irq_mask, ++ .irq_mask_ack = ralink_intc_irq_mask, ++ .irq_unmask = ralink_intc_irq_unmask, ++ .irq_eoi = ralink_intc_irq_unmask, ++}; ++ ++unsigned int get_c0_compare_int(void) ++{ ++ return RALINK_INTC_IRQ_BASE + RALINK_SOC_IRQ_TIMER; ++} ++ ++asmlinkage void plat_irq_dispatch(void) ++{ ++ unsigned long pending; ++ ++ pending = (read_c0_status() & read_c0_cause() & ST0_IM) >> 10; ++ ++ do_IRQ(pending + RALINK_INTC_IRQ_BASE - 1); ++} ++ ++static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) ++{ ++ irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops irq_domain_ops = { ++ .xlate = irq_domain_xlate_onecell, ++ .map = intc_map, ++}; ++ ++static int __init intc_of_init(struct device_node *node, ++ struct device_node *parent) ++{ ++ struct resource res; ++ struct irq_domain *domain; ++ ++ if (!of_property_read_u32_array(node, "ralink,intc-registers", ++ rt_intc_regs, 2)) ++ pr_info("intc: using register map from devicetree\n"); ++ ++ if (of_address_to_resource(node, 0, &res)) ++ panic("Failed to get intc memory range"); ++ ++ if (!request_mem_region(res.start, resource_size(&res), ++ res.name)) ++ pr_err("Failed to request intc memory"); ++ ++ rt_intc_membase = ioremap(res.start, ++ resource_size(&res)); ++ if (!rt_intc_membase) ++ panic("Failed to remap intc memory"); ++ ++ rt_intc_prio_w8(RALINK_SOC_IRQ_TIMER, 4); ++ rt_intc_prio_w8(24, 3); ++ rt_intc_prio_w8(21, 2); ++ rt_intc_prio_w8(15, 1); ++ ++ clear_c0_status(ST0_IM); ++ clear_c0_cause(CAUSEF_IP); ++ ++ domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT, ++ RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL); ++ if (!domain) ++ panic("Failed to add irqdomain"); ++ ++ set_c0_status(ST0_IM); ++ ++ return 0; ++} ++ ++static struct of_device_id __initdata of_irq_ids[] = { ++ { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, ++ { .compatible = "ralink,rt6855a-intc", .data = intc_of_init }, ++ {}, ++}; ++ ++void __init arch_init_irq(void) ++{ ++ of_irq_init(of_irq_ids); ++} +diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c +index 8126f1260407..bfc144887078 100644 +--- a/arch/mips/ralink/reset.c ++++ b/arch/mips/ralink/reset.c +@@ -22,6 +22,22 @@ + #define RSTCTL_RESET_PCI BIT(26) + #define RSTCTL_RESET_SYSTEM BIT(0) + ++#ifdef CONFIG_SOC_RT6855A ++#define CR_TIMER_BASE 0xBFBF0100 ++#define CR_TIMER_CTL ((char*)(CR_TIMER_BASE + 0x00)) ++#define CR_TIMER0_LDV (CR_TIMER_BASE + 0x04) ++ ++#define SYS_HCLK (23333/100) ++ ++#define TIMER_ENABLE 1 ++#define TIMER_DISABLE 0 ++#define TIMER_WDENABLE 1 ++#define TIMER_WDDISABLE 0 ++ ++static const u8 rt6855a_timer_no = 5; ++ ++#endif ++ + static int ralink_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) + { +@@ -90,7 +106,14 @@ static void ralink_restart(char *command) + } + + local_irq_disable(); ++#ifdef CONFIG_SOC_RT6855A ++ writel((100 /* ms */ * SYS_HCLK) * 1000 / 2, ++ (char*)(CR_TIMER0_LDV+rt6855a_timer_no*0x08)); ++ writel((TIMER_ENABLE << rt6855a_timer_no) | (TIMER_WDENABLE << 25), ++ CR_TIMER_CTL); ++#else + rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); ++#endif + unreachable(); + } + +diff --git a/arch/mips/ralink/rt6855a.c b/arch/mips/ralink/rt6855a.c +new file mode 100644 +index 000000000000..518a71a078cb +--- /dev/null ++++ b/arch/mips/ralink/rt6855a.c +@@ -0,0 +1,57 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) 2016 Imagination Technologies ++ * Author: Rafaël Carré <fun...@videolan.org> ++ */ ++ ++#include <linux/clk.h> ++#include <linux/clocksource.h> ++#include <linux/init.h> ++#include <linux/irqchip.h> ++#include <linux/of_clk.h> ++#include <linux/of_fdt.h> ++#include <linux/serial_reg.h> ++ ++#include <asm/bootinfo.h> ++#include <asm/fw/fw.h> ++#include <asm/irq_cpu.h> ++#include <asm/machine.h> ++#include <asm/mips-cps.h> ++#include <asm/prom.h> ++#include <asm/smp-ops.h> ++#include <asm/time.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#include "common.h" ++ ++void prom_soc_init(struct ralink_soc_info *soc_info) ++{ ++ soc_info->mem_size_min = 64; ++ soc_info->mem_size_max = 64; ++ soc_info->compatible = "ralink,rt6855a-soc"; ++ soc_info->mem_base = 0x20000; ++ ralink_soc = RT6855A_SOC; ++} ++ ++void __init ralink_of_remap(void) ++{ ++ rt_sysc_membase = plat_of_remap_node("ralink,rt6855a-sysc"); ++ rt_memc_membase = plat_of_remap_node("ralink,rt6855a-memc"); ++ ++ if (!rt_sysc_membase || !rt_memc_membase) ++ panic("Failed to remap core resources"); ++} ++ ++void __init ralink_clk_init(void) ++{ ++ unsigned long sys_rate = 233333333; ++ ++ /* TODO: move to DTS ? */ ++ ++ ralink_clk_add("cpu", 700000000); ++ ralink_clk_add("1fbf0100.watchdog", sys_rate); ++ ralink_clk_add("1fbf0000.uart", 40000000); ++ ralink_clk_add("1fb50000.ethernet", 700000000 / 2); ++ ralink_clk_add("1fbc0b00.spi", sys_rate); ++} +-- +2.27.0 + diff --git a/target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch b/target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch new file mode 100644 index 0000000000..972e969fc4 --- /dev/null +++ b/target/linux/ramips/patches-5.4/304-HACK-spi-mt7621-rt6855a-fix.patch @@ -0,0 +1,35 @@ +From cbc220c515f2b387462795b730b52dea96687885 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org> +Date: Wed, 23 Dec 2020 14:18:31 +0100 +Subject: [PATCH 2/5] HACK: spi-mt7621: rt6855a fix +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +TODO: no idea what this does or if it's needed on other targets +using this driver. + +Signed-off-by: Rafaël Carré <fun...@videolan.org> +--- + drivers/spi/spi-mt7621.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c +index 2c3b7a2a1ec7..58fb028ed776 100644 +--- a/drivers/spi/spi-mt7621.c ++++ b/drivers/spi/spi-mt7621.c +@@ -87,7 +87,10 @@ static void mt7621_spi_set_cs(struct spi_device *spi, int enable) + * reliably) + */ + master = mt7621_spi_read(rs, MT7621_SPI_MASTER); +- master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE; ++ master |= MASTER_MORE_BUFMODE; ++#ifndef CONFIG_SOC_RT6855A ++ master |= MASTER_RS_SLAVE_SEL; ++#endif + master &= ~MASTER_FULL_DUPLEX; + mt7621_spi_write(rs, MT7621_SPI_MASTER, master); + +-- +2.27.0 + diff --git a/target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch b/target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch new file mode 100644 index 0000000000..639b5f3b8f --- /dev/null +++ b/target/linux/ramips/patches-5.4/305-HACK-spi-mt7621.c-hardcode-frequency.patch @@ -0,0 +1,69 @@ +From 92687f92ce2ff9859a82327c97f929baafe24a66 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org> +Date: Wed, 23 Dec 2020 14:18:55 +0100 +Subject: [PATCH 3/5] HACK: spi-mt7621.c: hardcode frequency +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +TODO: use DTS + +Signed-off-by: Rafaël Carré <fun...@videolan.org> +--- + drivers/spi/spi-mt7621.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c +index 58fb028ed776..862303ec025b 100644 +--- a/drivers/spi/spi-mt7621.c ++++ b/drivers/spi/spi-mt7621.c +@@ -341,7 +341,7 @@ static int mt7621_spi_probe(struct platform_device *pdev) + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); +- ++#if 0 + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", +@@ -352,7 +352,7 @@ static int mt7621_spi_probe(struct platform_device *pdev) + status = clk_prepare_enable(clk); + if (status) + return status; +- ++#endif + master = spi_alloc_master(&pdev->dev, sizeof(*rs)); + if (!master) { + dev_info(&pdev->dev, "master allocation failed\n"); +@@ -373,16 +373,16 @@ static int mt7621_spi_probe(struct platform_device *pdev) + rs->base = base; + rs->clk = clk; + rs->master = master; +- rs->sys_freq = clk_get_rate(rs->clk); ++ rs->sys_freq = 233333333;//clk_get_rate(rs->clk); + rs->pending_write = 0; + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq); + +- ret = device_reset(&pdev->dev); ++/* ret = device_reset(&pdev->dev); + if (ret) { + dev_err(&pdev->dev, "SPI reset failed!\n"); + return ret; + } +- ++*/ + return devm_spi_register_controller(&pdev->dev, master); + } + +@@ -394,7 +394,7 @@ static int mt7621_spi_remove(struct platform_device *pdev) + master = dev_get_drvdata(&pdev->dev); + rs = spi_controller_get_devdata(master); + +- clk_disable_unprepare(rs->clk); ++// clk_disable_unprepare(rs->clk); + + return 0; + } +-- +2.27.0 + diff --git a/target/linux/ramips/patches-5.4/306-RT6855A-add-watchdog.patch b/target/linux/ramips/patches-5.4/306-RT6855A-add-watchdog.patch new file mode 100644 index 0000000000..3b9fe9dfd1 --- /dev/null +++ b/target/linux/ramips/patches-5.4/306-RT6855A-add-watchdog.patch @@ -0,0 +1,236 @@ +From 7f93281b983b92e4102379d8f593fc54811a8305 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org> +Date: Wed, 23 Dec 2020 14:21:33 +0100 +Subject: [PATCH 4/5] RT6855A: add watchdog +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +TODO: correct frequencies, they seem wrong + +Driver is based on mt7621_wdt.c + +Signed-off-by: Rafaël Carré <fun...@videolan.org> +--- + drivers/watchdog/Kconfig | 7 ++ + drivers/watchdog/Makefile | 1 + + drivers/watchdog/rt6855a_wdt.c | 177 +++++++++++++++++++++++++++++++++ + 3 files changed, 185 insertions(+) + create mode 100644 drivers/watchdog/rt6855a_wdt.c + +diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig +index 58e7c100b6ad..31f9ded03634 100644 +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1795,6 +1795,13 @@ config RALINK_WDT + help + Hardware driver for the Ralink SoC Watchdog Timer. + ++config RT6855A_WDT ++ tristate "Ralink RT6855A SoC watchdog" ++ select WATCHDOG_CORE ++ depends on RALINK ++ help ++ Hardware driver for the Ralink RT6855A SoC Watchdog Timer. ++ + config MT7621_WDT + tristate "Mediatek SoC watchdog" + select WATCHDOG_CORE +diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile +index 2ee352bf3372..ce8a350189c9 100644 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -167,6 +167,7 @@ octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o + obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o + obj-$(CONFIG_LOONGSON1_WDT) += loongson1_wdt.o + obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o ++obj-$(CONFIG_RT6855A_WDT) += rt6855a_wdt.o + obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o + obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o + obj-$(CONFIG_PIC32_WDT) += pic32-wdt.o +diff --git a/drivers/watchdog/rt6855a_wdt.c b/drivers/watchdog/rt6855a_wdt.c +new file mode 100644 +index 000000000000..33d573afa529 +--- /dev/null ++++ b/drivers/watchdog/rt6855a_wdt.c +@@ -0,0 +1,177 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Ralink RT6855A built-in hardware watchdog timer ++ * ++ * Copyright (C) 2014 John Crispin <j...@phrozen.org> ++ * ++ * This driver was based on: drivers/watchdog/mt7621_wdt.c ++ */ ++ ++#include <linux/clk.h> ++#include <linux/reset.h> ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/watchdog.h> ++#include <linux/moduleparam.h> ++#include <linux/platform_device.h> ++#include <linux/mod_devicetable.h> ++ ++#include <asm/mach-ralink/ralink_regs.h> ++ ++#define TIMER_REG_TMRSTAT 0x38 ++#define TIMER_REG_TMR1LOAD 0x2C ++#define TIMER_REG_TMR1CTL 0x00 ++ ++#define TMR1CTL_ENABLE (BIT(5)|BIT(25)) ++#define TMR1CTL_RESTART BIT(0) ++ ++static void __iomem *rt6855a_wdt_base; ++static struct reset_control *rt6855a_wdt_reset; ++ ++static bool nowayout = WATCHDOG_NOWAYOUT; ++module_param(nowayout, bool, 0); ++MODULE_PARM_DESC(nowayout, ++ "Watchdog cannot be stopped once started (default=" ++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); ++ ++static inline void rt_wdt_w32(unsigned reg, u32 val) ++{ ++ iowrite32(val, rt6855a_wdt_base + reg); ++} ++ ++static inline u32 rt_wdt_r32(unsigned reg) ++{ ++ return ioread32(rt6855a_wdt_base + reg); ++} ++ ++static int rt6855a_wdt_ping(struct watchdog_device *w) ++{ ++ rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART); ++ ++ return 0; ++} ++ ++static int rt6855a_wdt_set_timeout(struct watchdog_device *w, unsigned int t) ++{ ++ w->timeout = t; ++ rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000 * (23333/100)*1000/2); ++ rt6855a_wdt_ping(w); ++ ++ return 0; ++} ++ ++static int rt6855a_wdt_start(struct watchdog_device *w) ++{ ++ u32 t; ++ ++ rt6855a_wdt_set_timeout(w, w->timeout); ++ ++ t = rt_wdt_r32(TIMER_REG_TMR1CTL); ++ t |= TMR1CTL_ENABLE; ++ rt_wdt_w32(TIMER_REG_TMR1CTL, t); ++ ++ return 0; ++} ++ ++static int rt6855a_wdt_stop(struct watchdog_device *w) ++{ ++ u32 t; ++ ++ rt6855a_wdt_ping(w); ++ ++ t = rt_wdt_r32(TIMER_REG_TMR1CTL); ++ t &= ~TMR1CTL_ENABLE; ++ rt_wdt_w32(TIMER_REG_TMR1CTL, t); ++ ++ return 0; ++} ++ ++static int rt6855a_wdt_bootcause(void) ++{ ++ return 0; ++} ++ ++static int rt6855a_wdt_is_running(struct watchdog_device *w) ++{ ++ return !!(rt_wdt_r32(TIMER_REG_TMR1CTL) & TMR1CTL_ENABLE); ++} ++ ++static const struct watchdog_info rt6855a_wdt_info = { ++ .identity = "Ralink Watchdog", ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, ++}; ++ ++static const struct watchdog_ops rt6855a_wdt_ops = { ++ .owner = THIS_MODULE, ++ .start = rt6855a_wdt_start, ++ .stop = rt6855a_wdt_stop, ++ .ping = rt6855a_wdt_ping, ++ .set_timeout = rt6855a_wdt_set_timeout, ++}; ++ ++static struct watchdog_device rt6855a_wdt_dev = { ++ .info = &rt6855a_wdt_info, ++ .ops = &rt6855a_wdt_ops, ++ .min_timeout = 1, ++ .max_timeout = 0xfffffffful / (1000*23333/100*1000/2), ++}; ++ ++static int rt6855a_wdt_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ rt6855a_wdt_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rt6855a_wdt_base)) ++ return PTR_ERR(rt6855a_wdt_base); ++ ++ rt6855a_wdt_reset = devm_reset_control_get_exclusive(dev, NULL); ++ if (!IS_ERR(rt6855a_wdt_reset)) ++ reset_control_deassert(rt6855a_wdt_reset); ++ ++ rt6855a_wdt_dev.bootstatus = rt6855a_wdt_bootcause(); ++ ++ watchdog_init_timeout(&rt6855a_wdt_dev, rt6855a_wdt_dev.max_timeout, ++ dev); ++ watchdog_set_nowayout(&rt6855a_wdt_dev, nowayout); ++ if (rt6855a_wdt_is_running(&rt6855a_wdt_dev)) { ++ /* ++ * Make sure to apply timeout from watchdog core, taking ++ * the prescaler of this driver here into account (the ++ * boot loader might be using a different prescaler). ++ * ++ * To avoid spurious resets because of different scaling, ++ * we first disable the watchdog, set the new prescaler ++ * and timeout, and then re-enable the watchdog. ++ */ ++ rt6855a_wdt_stop(&rt6855a_wdt_dev); ++ rt6855a_wdt_start(&rt6855a_wdt_dev); ++ set_bit(WDOG_HW_RUNNING, &rt6855a_wdt_dev.status); ++ } ++ ++ return devm_watchdog_register_device(dev, &rt6855a_wdt_dev); ++} ++ ++static void rt6855a_wdt_shutdown(struct platform_device *pdev) ++{ ++ rt6855a_wdt_stop(&rt6855a_wdt_dev); ++} ++ ++static const struct of_device_id rt6855a_wdt_match[] = { ++ { .compatible = "ralink,rt6855a-wdt" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, rt6855a_wdt_match); ++ ++static struct platform_driver rt6855a_wdt_driver = { ++ .probe = rt6855a_wdt_probe, ++ .shutdown = rt6855a_wdt_shutdown, ++ .driver = { ++ .name = KBUILD_MODNAME, ++ .of_match_table = rt6855a_wdt_match, ++ }, ++}; ++ ++module_platform_driver(rt6855a_wdt_driver); ++ ++MODULE_DESCRIPTION("Ralink RT6855a hardware watchdog driver"); ++MODULE_AUTHOR("Rafaël Carré <fun...@videolan.org>"); ++MODULE_LICENSE("GPL v2"); +-- +2.27.0 + diff --git a/target/linux/ramips/patches-5.4/307-HACK-RT6855A-Use-Linksys-provided-PCI-driver.patch b/target/linux/ramips/patches-5.4/307-HACK-RT6855A-Use-Linksys-provided-PCI-driver.patch new file mode 100644 index 0000000000..c63cbd30dc --- /dev/null +++ b/target/linux/ramips/patches-5.4/307-HACK-RT6855A-Use-Linksys-provided-PCI-driver.patch @@ -0,0 +1,1884 @@ +From d3e2c4b03d57b3edb23993ca978214a22fe3c8c4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Rafa=C3=ABl=20Carr=C3=A9?= <fun...@videolan.org> +Date: Wed, 23 Dec 2020 14:25:59 +0100 +Subject: [PATCH] HACK: RT6855A: Use Linksys provided PCI driver +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This should be replaced by modifications to existing Ralink PCI drivers +This works for now, permitting to test WLAN + +TODO: remove HACK in pci-legacy.c + +Source: https://downloads.linksys.com/downloads/gpl/WAP300N_v1.0.04_build_5.tgz + +Signed-off-by: Rafaël Carré <fun...@videolan.org> +--- + arch/mips/pci/pci-legacy.c | 4 +- + arch/mips/ralink/Makefile | 2 +- + arch/mips/ralink/eureka_ep430.h | 186 ++++++ + arch/mips/ralink/pci.c | 1067 +++++++++++++++++++++++++++++++ + arch/mips/ralink/rt_mmap.h | 551 ++++++++++++++++ + 5 files changed, 1807 insertions(+), 3 deletions(-) + create mode 100755 arch/mips/ralink/eureka_ep430.h + create mode 100644 arch/mips/ralink/pci.c + create mode 100644 arch/mips/ralink/rt_mmap.h + +diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c +index 39052de915f3..d6e0cd32fe05 100644 +--- a/arch/mips/pci/pci-legacy.c ++++ b/arch/mips/pci/pci-legacy.c +@@ -195,12 +195,12 @@ void register_pci_controller(struct pci_controller *hose) + parent = hose->io_resource->parent; + if (!parent) + parent = &ioport_resource; +- ++#if 0 + if (request_resource(parent, hose->io_resource) < 0) { + release_resource(hose->mem_resource); + goto out; + } +- ++#endif + INIT_LIST_HEAD(&hose->list); + list_add_tail(&hose->list, &controllers); + +diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile +index 2bb8ddd69dff..38fa44914d73 100644 +--- a/arch/mips/ralink/Makefile ++++ b/arch/mips/ralink/Makefile +@@ -25,7 +25,7 @@ obj-$(CONFIG_SOC_RT305X) += rt305x.o + obj-$(CONFIG_SOC_RT3883) += rt3883.o + obj-$(CONFIG_SOC_MT7620) += mt7620.o + obj-$(CONFIG_SOC_MT7621) += mt7621.o +-obj-$(CONFIG_SOC_RT6855A) += rt6855a.o irq-rt6855a.o ++obj-$(CONFIG_SOC_RT6855A) += rt6855a.o irq-rt6855a.o pci.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +diff --git a/arch/mips/ralink/eureka_ep430.h b/arch/mips/ralink/eureka_ep430.h +new file mode 100755 +index 000000000000..8eac5e5016a3 +--- /dev/null ++++ b/arch/mips/ralink/eureka_ep430.h +@@ -0,0 +1,186 @@ ++/************************************************************************** ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#define CONFIG_RALINK_RT6855A ++#ifndef _EUREKA_EP430_H ++#define _EUREKA_EP430_H ++ ++ ++#include <asm/addrspace.h> /* for KSEG1ADDR() */ ++#include <asm/byteorder.h> /* for cpu_to_le32() */ ++#include "rt_mmap.h" ++ ++ ++/* ++ * Because of an error/peculiarity in the Galileo chip, we need to swap the ++ * bytes when running bigendian. ++ */ ++ ++#define MV_WRITE(ofs, data) \ ++ *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data) ++#define MV_READ(ofs, data) \ ++ *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) ++#define MV_READ_DATA(ofs) \ ++ le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs))) ++ ++#define MV_WRITE_16(ofs, data) \ ++ *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data) ++#define MV_READ_16(ofs, data) \ ++ *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs))) ++ ++#define MV_WRITE_8(ofs, data) \ ++ *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data ++#define MV_READ_8(ofs, data) \ ++ *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) ++ ++#define MV_SET_REG_BITS(ofs,bits) \ ++ (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits)) ++#define MV_RESET_REG_BITS(ofs,bits) \ ++ (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits)) ++ ++#define RALINK_PCI_CONFIG_ADDR 0x20 ++#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 ++ ++#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883) ++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) ++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004) ++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008) ++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) ++#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010) ++#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018) ++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C) ++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028) ++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C) ++#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030) ++#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034) ++#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038) ++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080) ++#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050) ++ ++#elif defined(CONFIG_RALINK_RT3883) ++ ++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) ++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004) ++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008) ++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) ++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C) ++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028) ++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C) ++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080) ++ ++/* ++PCI0 --> PCI ++PCI1 --> PCIe ++*/ ++#define RT3883_PCI_OFFSET 0x1000 ++#define RT3883_PCIE_OFFSET 0x2000 ++ ++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010) ++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018) ++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030) ++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034) ++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038) ++ ++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010) ++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018) ++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030) ++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034) ++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038) ++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050) ++ ++#elif defined(CONFIG_RALINK_RT6855) ++ ++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) ++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004) ++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008) ++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) ++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C) ++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028) ++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C) ++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080) ++ ++/* ++PCI0 --> PCIe 0 ++PCI1 --> PCIe 1 ++*/ ++#define RT6855_PCIE0_OFFSET 0x2000 ++#define RT6855_PCIE1_OFFSET 0x3000 ++ ++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010) ++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018) ++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030) ++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) ++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) ++#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) ++ ++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) ++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) ++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030) ++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) ++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) ++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) ++ ++#elif defined(CONFIG_RALINK_RT6855A) ++ ++#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000) ++#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004) ++#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008) ++#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C) ++#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C) ++#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028) ++#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C) ++#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080) ++ ++/* ++PCI0 --> PCIe 0 ++PCI1 --> PCIe 1 ++*/ ++#define RT6855_PCIE0_OFFSET 0x2000 ++#define RT6855_PCIE1_OFFSET 0x3000 ++ ++#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010) ++#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018) ++#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030) ++#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034) ++#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038) ++#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050) ++#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064) ++ ++ ++#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010) ++#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018) ++#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030) ++#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034) ++#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038) ++#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050) ++#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064) ++ ++#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350) ++#else ++#error "undefined in PCI" ++#endif ++ ++#endif +diff --git a/arch/mips/ralink/pci.c b/arch/mips/ralink/pci.c +new file mode 100644 +index 000000000000..ba60b9ad77ca +--- /dev/null ++++ b/arch/mips/ralink/pci.c +@@ -0,0 +1,1067 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * PCI init for Ralink solution ++ * ++ * Copyright 2007 Ralink Inc. (bruce_ch...@ralinktech.com.tw) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2007 Bruce Chang ++ * Initial Release ++ * ++ * May 2009 Bruce Chang ++ * support RT2880/RT3883 PCIe ++ * ++ * Feb 2011 Bruce Chang ++ * support RT6855 PCI and PCIe architecture ++ * ++ * Sep 2011 Bruce Chang ++ * support RT6855A PCIe architecture ++ * ++ ************************************************************************** ++ */ ++ ++ ++#define CONFIG_RT6855A_PCIE_PORT01_ENABLE ++#include <linux/types.h> ++#include <linux/pci.h> ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include <linux/version.h> ++#include <asm/pci.h> ++#include <asm/io.h> ++#include "eureka_ep430.h" ++#include <linux/init.h> ++#include <linux/mod_devicetable.h> ++#include <linux/delay.h> ++//#include <asm/rt2880/surfboardint.h> ++ ++#define RALINK_INT_PCIE0 32 /* PCIE0 */ ++#define RALINK_INT_PCIE1 31 /* PCIE1 */ ++ ++ ++ ++#ifdef CONFIG_PCI ++ ++/* ++ * These functions and structures provide the BIOS scan and mapping of the PCI ++ * devices. ++ */ ++ ++#define RALINK_PCI_MM_MAP_BASE 0x20000000 ++ ++#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_RT6855) ++#define RALINK_PCI_IO_MAP_BASE 0x10160000 ++#elif defined(CONFIG_RALINK_RT6855A) ++#define RALINK_PCI_IO_MAP_BASE 0x1f600000 ++#else ++#define RALINK_PCI_IO_MAP_BASE 0x00460000 ++#endif ++ ++#define RALINK_SYSTEM_CONTROL_BASE 0xb0000000 ++#define RALINK_SYSCFG1 *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x14) ++#define RALINK_CLKCFG1 *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x30) ++#define RALINK_RSTCTRL *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x34) ++#define RALINK_GPIOMODE *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x60) ++#define RALINK_PCIE_CLK_GEN *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c) ++#define RALINK_PCIE_CLK_GEN1 *(unsigned long *)(RALINK_SYSTEM_CONTROL_BASE + 0x80) ++//RALINK_SYSCFG1 bit ++#define RALINK_PCI_HOST_MODE_EN (1<<7) ++#define RALINK_PCIE_RC_MODE_EN (1<<8) ++//RALINK_RSTCTRL bit ++#define RALINK_PCIE_RST (1<<23) ++#define RALINK_PCI_RST (1<<24) ++//RALINK_CLKCFG1 bit ++#define RALINK_PCI_CLK_EN (1<<19) ++#define RALINK_PCIE_CLK_EN (1<<21) ++//RALINK_GPIOMODE bit ++#define PCI_SLOTx2 (1<<11) ++#define PCI_SLOTx1 (2<<11) ++ ++ ++#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) ++#define MEMORY_BASE 0x0 ++#else ++#define MEMORY_BASE 0x08000000 ++#endif ++ ++#if defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) ++ //pcie_disable = 0 mean there is a card on this slot ++ //pcie_disable = 1 mean there is no card on this slot ++ int pcie0_disable =0; ++ int pcie1_disable =0; ++#endif ++//extern pci_probe_only; ++ ++void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val); ++void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val); ++ ++#if 1 ++ ++#define PCI_ACCESS_READ_1 0 ++#define PCI_ACCESS_READ_2 1 ++#define PCI_ACCESS_READ_4 2 ++#define PCI_ACCESS_WRITE_1 3 ++#define PCI_ACCESS_WRITE_2 4 ++#define PCI_ACCESS_WRITE_4 5 ++ ++static int config_access(unsigned char access_type, struct pci_bus *bus, ++ unsigned int devfn, unsigned char where, ++ u32 * data) ++{ ++ unsigned int slot = PCI_SLOT(devfn); ++ u8 func = PCI_FUNC(devfn); ++ uint32_t address_reg, data_reg; ++ unsigned int address; ++ ++ address_reg = RALINK_PCI_CONFIG_ADDR; ++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; ++ ++ /* Setup address */ ++#if defined(CONFIG_RALINK_RT2883) ++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc)| 0x1; ++#elif defined (CONFIG_RALINK_RT3883) ++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; ++#elif defined (CONFIG_RALINK_RT6855) ++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; ++#elif defined(CONFIG_RALINK_RT6855A) ++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc); ++#else ++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000; ++#endif ++ /* start the configuration cycle */ ++ MV_WRITE(address_reg, address); ++ ++ switch(access_type) { ++ case PCI_ACCESS_WRITE_1: ++ MV_WRITE_8(data_reg+(where&0x3), *data); ++ break; ++ case PCI_ACCESS_WRITE_2: ++ MV_WRITE_16(data_reg+(where&0x3), *data); ++ break; ++ case PCI_ACCESS_WRITE_4: ++ MV_WRITE(data_reg, *data); ++ break; ++ case PCI_ACCESS_READ_1: ++ MV_READ_8( data_reg+(where&0x3), data); ++ break; ++ case PCI_ACCESS_READ_2: ++ MV_READ_16(data_reg+(where&0x3), data); ++ break; ++ case PCI_ACCESS_READ_4: ++ MV_READ(data_reg, data); ++ break; ++ default: ++ printk("no specify access type\n"); ++ break; ++ } ++ //if (bus->number==1&&where==0x30){ ++ //printk("_%x->[%x][%x][%x][%x]=%x\n",access_type,bus->number, slot, func, where, *data); ++ //} ++ return 0; ++} ++ ++ ++ ++static int read_config_byte(struct pci_bus *bus, unsigned int devfn, ++ int where, u8 * val) ++{ ++ //u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned char)where, (u32 *)val); ++ //*val = (data >> ((where & 3) << 3)) & 0xff; ++ return ret; ++} ++ ++static int read_config_word(struct pci_bus *bus, unsigned int devfn, ++ int where, u16 * val) ++{ ++ //u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned char)where, (u32 *)val); ++ //*val = (data >> ((where & 3) << 3)) & 0xffff; ++ return ret; ++} ++ ++static int read_config_dword(struct pci_bus *bus, unsigned int devfn, ++ int where, u32 * val) ++{ ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned char)where, (u32 *)val); ++ return ret; ++} ++static int ++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, ++ u8 val) ++{ ++ if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned char)where, (u32 *)&val)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ++write_config_word(struct pci_bus *bus, unsigned int devfn, int where, ++ u16 val) ++{ ++ if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val)) ++ return -1; ++ ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, ++ u32 val) ++{ ++ if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++#else ++#define PCI_ACCESS_READ 0 ++#define PCI_ACCESS_WRITE 1 ++ ++static int config_access(unsigned char access_type, struct pci_bus *bus, ++ unsigned int devfn, unsigned char where, ++ u32 * data) ++{ ++ unsigned int slot = PCI_SLOT(devfn); ++ u8 func = PCI_FUNC(devfn); ++ uint32_t address_reg, data_reg; ++ unsigned int address; ++ ++ address_reg = RALINK_PCI_CONFIG_ADDR; ++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; ++ ++ /* Setup address */ ++#ifdef CONFIG_RALINK_RT2883 ++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc)| 0x1; ++#elif CONFIG_RALINK_RT3883 ++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; ++#elif defined (CONFIG_RALINK_RT6855) ++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000; ++#elif defined(CONFIG_RALINK_RT6855A) ++ address = (bus->number << 24) | (slot << 19) | (func << 16) | (where & 0xfc); ++#else ++ address = (bus->number << 16) | (slot << 11) | (func << 8) | (where& 0xfc) | 0x80000000; ++#endif ++ /* start the configuration cycle */ ++ MV_WRITE(address_reg, address); ++ ++ if (access_type == PCI_ACCESS_WRITE){ ++ MV_WRITE(data_reg, *data); ++ }else{ ++ MV_READ(data_reg, data); ++ } ++ //printk("-%x->[%x][%x][%x][%x]=%x\n",access_type,bus->number, slot, func, where, *data); ++ return 0; ++} ++ ++ ++ ++static int read_config_byte(struct pci_bus *bus, unsigned int devfn, ++ int where, u8 * val) ++{ ++ u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); ++ *val = (data >> ((where & 3) << 3)) & 0xff; ++ return ret; ++} ++ ++static int read_config_word(struct pci_bus *bus, unsigned int devfn, ++ int where, u16 * val) ++{ ++ u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); ++ *val = (data >> ((where & 3) << 3)) & 0xffff; ++ return ret; ++} ++ ++static int read_config_dword(struct pci_bus *bus, unsigned int devfn, ++ int where, u32 * val) ++{ ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); ++ return ret; ++} ++static int ++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, ++ u8 val) ++{ ++ u32 data = 0; ++ ++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) ++ return -1; ++ ++ data = (data & ~(0xff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ++write_config_word(struct pci_bus *bus, unsigned int devfn, int where, ++ u16 val) ++{ ++ u32 data = 0; ++ ++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) ++ return -1; ++ ++ data = (data & ~(0xffff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) ++ return -1; ++ ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int ++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, ++ u32 val) ++{ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++#endif ++ ++static int pci_config_read(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 * val) ++{ ++ switch (size) { ++ case 1: ++ return read_config_byte(bus, devfn, where, (u8 *) val); ++ case 2: ++ return read_config_word(bus, devfn, where, (u16 *) val); ++ default: ++ return read_config_dword(bus, devfn, where, val); ++ } ++} ++ ++static int pci_config_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 val) ++{ ++ switch (size) { ++ case 1: ++ return write_config_byte(bus, devfn, where, (u8) val); ++ case 2: ++ return write_config_word(bus, devfn, where, (u16) val); ++ default: ++ return write_config_dword(bus, devfn, where, val); ++ } ++} ++ ++ ++/* ++ * General-purpose PCI functions. ++ */ ++ ++struct pci_ops rt2880_pci_ops= { ++ .read = pci_config_read, ++ .write = pci_config_write, ++}; ++ ++static struct resource rt2880_res_pci_mem1 = { ++ .name = "PCI MEM1", ++ .start = RALINK_PCI_MM_MAP_BASE, ++ .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)), ++ .flags = IORESOURCE_MEM, ++}; ++static struct resource rt2880_res_pci_io1 = { ++ .name = "PCI I/O1", ++ .start = RALINK_PCI_IO_MAP_BASE, ++ .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)), ++ .flags = IORESOURCE_IO, ++}; ++ ++struct pci_controller rt2880_controller = { ++ .pci_ops = &rt2880_pci_ops, ++ .mem_resource = &rt2880_res_pci_mem1, ++ .io_resource = &rt2880_res_pci_io1, ++ .mem_offset = 0x00000000UL, ++ .io_offset = 0x00000000UL, ++}; ++ ++void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val) ++{ ++ unsigned long address_reg, data_reg, address; ++ ++ address_reg = RALINK_PCI_CONFIG_ADDR; ++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; ++ ++ /* set addr */ ++#if defined (CONFIG_RALINK_RT2883) ++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg & 0xfc); ++#elif defined (CONFIG_RALINK_RT3883) ++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ; ++#elif defined (CONFIG_RALINK_RT6855) ++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ; ++#elif defined (CONFIG_RALINK_RT6855A) ++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg& 0xfc); ++#else ++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ; ++#endif ++ ++ /* start the configuration cycle */ ++ MV_WRITE(address_reg, address); ++ /* read the data */ ++ MV_READ(data_reg, val); ++ return; ++} ++ ++void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val) ++{ ++ unsigned long address_reg, data_reg, address; ++ ++ address_reg = RALINK_PCI_CONFIG_ADDR; ++ data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; ++ ++ /* set addr */ ++#if defined (CONFIG_RALINK_RT2883) ++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg & 0xfc); ++#elif defined (CONFIG_RALINK_RT3883) ++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ; ++#elif defined (CONFIG_RALINK_RT6855) ++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg& 0xfc) | 0x80000000 ; ++#elif defined (CONFIG_RALINK_RT6855A) ++ address = (bus << 24) | (dev << 19) | (func << 16) | (reg& 0xfc); ++#else ++ address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ; ++#endif ++ /* start the configuration cycle */ ++ MV_WRITE(address_reg, address); ++ /* read the data */ ++ MV_WRITE(data_reg, val); ++ return; ++} ++ ++ ++int pcibios_map_irq(const struct pci_dev *d, u8 slot, u8 pin) ++{ ++ struct pci_dev *dev = (struct pci_dev *)d; ++ u16 cmd; ++ u32 val; ++ struct resource *res; ++ int i; ++#ifdef CONFIG_RALINK_RT2883 ++ if (dev->bus->number > 1) { ++ printk("bus>1\n"); ++ return 0; ++ } ++ if (slot > 0) { ++ printk("slot=%d >0\n", slot); ++ return 0; ++ } ++#elif defined (CONFIG_RALINK_RT2880) ++ if (dev->bus->number != 0) { ++ return 0; ++ } ++#else ++#endif ++ ++ printk("** bus= %x, slot=0x%x\n",dev->bus->number, slot); ++#ifdef CONFIG_RALINK_RT3883 ++ if((dev->bus->number ==0) && (slot == 0)) { ++ RALINK_PCI0_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE ++ RALINK_PCI0_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE ++ RALINK_PCI1_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE ++ RALINK_PCI1_BAR0SETUP_ADDR = 0x03FF0001; //open 3FF:64M; ENABLE ++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val); ++ printk("BAR0 at slot 0 = %x\n", val); ++// dev->irq = 0; ++ printk("bus=0, slot = 0x%x\n", slot); ++ res = &dev->resource[0]; ++ res->start = MEMORY_BASE; ++ res->end = MEMORY_BASE + 0x01ffffff; ++ for(i=0;i<16;i++){ ++ read_config(0, 0, 0, i<<2, (unsigned long *)&val); ++ printk("P2P(PCI) 0x%02x = %08x\n", i<<2, val); ++ } ++ dev->irq = 0; ++ }else if((dev->bus->number ==0) && (slot == 0x1)){ ++ write_config(0, 1, 0, 0x1c, 0x00000101); ++ for(i=0;i<16;i++){ ++ read_config(0, 1, 0, i<<2, (unsigned long *)&val); ++ printk("P2P(PCIe) 0x%02x = %08x\n", i<<2, val); ++ } ++ }else if((dev->bus->number ==0) && (slot == 0x11)){ ++ printk("bus=0, slot = 0x%x\n", slot); ++ for(i=0;i<16;i++){ ++ read_config(0, 0x11, 0, i<<2, (unsigned long *)&val); ++ printk("dev I(PCI) 0x%02x = %08x\n", i<<2, val); ++ } ++ dev->irq = 2; ++ }else if((dev->bus->number ==0) && (slot == 0x12)){ ++ printk("bus=0, slot = 0x%x\n", slot); ++ for(i=0;i<16;i++){ ++ read_config(0, 0x12, 0, i<<2, (unsigned long *)&val); ++ printk("dev II(PCI) 0x%02x = %08x\n", i<<2, val); ++ } ++ dev->irq = 15; ++ }else if((dev->bus->number ==1) ){ ++ printk("bus=1, slot = 0x%x\n", slot); ++ for(i=0;i<16;i++){ ++ read_config(1, 0, 0, i<<2, (unsigned long *)&val); ++ printk("dev III(PCIe) 0x%02x = %08x\n", i<<2, val); ++ } ++ dev->irq = 16; ++ }else{ ++ return 0; ++ } ++#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) ++ if((dev->bus->number ==0) && (slot == 0)) { ++ RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G ++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val); ++ //write_config(0, 0, 0, 0x1c, 0x00000101); ++ printk("BAR0 at slot 0 = %x\n", val); ++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot); ++#if 0 ++ res = &dev->resource[0]; ++ res->start = MEMORY_BASE; ++ res->end = MEMORY_BASE + 0x03ffffff; ++ //dev->irq = RALINK_INT_PCIE0; ++ for(i=0;i<16;i++){ ++ read_config(0, 0, 0, i<<2, &val); ++ printk("P2P(PCIe0) 0x%02x = %08x\n", i<<2, val); ++ } ++#endif ++ }else if((dev->bus->number ==0) && (slot == 0x1)){ ++ RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G ++ write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val); ++ //write_config(0, 1, 0, 0x1c, 0x00000101); ++ printk("BAR0 at slot 1 = %x\n", val); ++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot); ++#if 0 ++ res = &dev->resource[0]; ++ res->start = MEMORY_BASE; ++ res->end = MEMORY_BASE + 0x03ffffff; ++ //dev->irq = RALINK_INT_PCIE1; ++ for(i=0;i<16;i++){ ++ read_config(0, 1, 0, i<<2, &val); ++ printk("P2P(PCIe1) 0x%02x = %08x\n", i<<2, val); ++ } ++#endif ++ }else if((dev->bus->number ==1) && (slot == 0x0)){ ++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot); ++ dev->irq = RALINK_INT_PCIE0; ++#if 0 ++ for(i=0;i<16;i++){ ++ read_config(1, 0, 0, i<<2, &val); ++ printk("dev I(PCIe0) 0x%02x = %08x\n", i<<2, val); ++ } ++#endif ++ }else if((dev->bus->number ==1) && (slot == 0x1)){ ++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot); ++ dev->irq = RALINK_INT_PCIE1; ++ }else if((dev->bus->number ==2) && (slot == 0x0)){ ++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot); ++ dev->irq = RALINK_INT_PCIE1; ++#if 0 ++ for(i=0;i<16;i++){ ++ read_config(2, 0, 0, i<<2, &val); ++ printk("dev II(PCIe1) 0x%02x = %08x\n", i<<2, val); ++ } ++#endif ++ }else if((dev->bus->number ==2) && (slot == 0x1)){ ++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot); ++ dev->irq = RALINK_INT_PCIE1; ++ }else{ ++ printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot); ++ return 0; ++ } ++#elif defined (CONFIG_RALINK_RT2883) ++ if((dev->bus->number ==0) && (slot == 0)) { ++ RALINK_PCI_BAR0SETUP_ADDR = 0x01FF0001; //open 1FF:32M; ENABLE ++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val); ++ printk("BAR0 at slot 0 = %x\n", val); ++// dev->irq = 0; ++ printk("bus=0, slot = 0x%x\n", slot); ++ res = &dev->resource[0]; ++ res->start = MEMORY_BASE; ++ res->end = MEMORY_BASE + 0x01ffffff; ++ for(i=0;i<16;i++){ ++ read_config(0, 0, 0, i<<2, &val); ++ printk("pci-to-pci 0x%02x = %08x\n", i<<2, val); ++ } ++ dev->irq = 0; ++ }else if((dev->bus->number ==1)){ ++ printk("bus=1, slot = 0x%x\n", slot); ++ for(i=0;i<16;i++){ ++ read_config(1, slot, 0, (i)<<2, &val); ++ printk("bus 1 dev %d fun 0: 0x%02x = %08x\n", slot, i<<2, val); ++ } ++ dev->irq = 2; ++ }else{ ++ return 0; ++ } ++#else //RT2880 ++ if(slot == 0) { ++ printk("*************************************************************\n"); ++ RALINK_PCI_BAR0SETUP_ADDR = 0x07FF0001; ++ printk("MEMORY_BASE = %x\n", MEMORY_BASE); ++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val); ++ dev->irq = 0; ++ res = &dev->resource[0]; ++ res->start = 0x08000000; ++ res->end = 0x09ffffff; ++ printk("BAR0 at slot 0 = %x\n", val); ++ }else if(slot ==0x11){ ++ dev->irq = 2; ++ }else if(slot==0x12){ ++ dev->irq = 15; ++ }else{ ++ return 0; ++ } ++#endif ++ ++ for(i=0;i<6;i++){ ++ res = &dev->resource[i]; ++ printk("res[%d]->start = %x\n", i, res->start); ++ printk("res[%d]->end = %x\n", i, res->end); ++ } ++ ++ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14 ++ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10 ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++//FIXME ++#if defined(CONFIG_RALINK_RT2883) || defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) ++ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; ++#else ++ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR | ++ PCI_COMMAND_WAIT | PCI_COMMAND_PARITY; ++#endif ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); ++ //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq); ++ return (dev->irq); ++} ++ ++int init_ralink_pci(void) ++{ ++ unsigned long val = 0; ++#if 0 /*CONFIG_RALINK_RT6855*/ ++ int i; ++#endif ++ ++#if defined(CONFIG_PCIE_ONLY) || defined(CONFIG_PCIE_PCI_CONCURRENT) ++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST); ++ RALINK_SYSCFG1 &= ~(0x30); ++ RALINK_SYSCFG1 |= (2<<4); ++ RALINK_PCIE_CLK_GEN &= 0x7fffffff; ++ RALINK_PCIE_CLK_GEN1 &= 0x80ffffff; ++ RALINK_PCIE_CLK_GEN1 |= 0xa << 24; ++ RALINK_PCIE_CLK_GEN |= 0x80000000; ++ mdelay(50); ++ RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST); ++#endif ++ ++#ifdef CONFIG_RALINK_RT3883 ++#if 0 ++ printk("before\n"); ++ printk("RALINK_GPIOMODE = %x\n", RALINK_GPIOMODE); ++ printk("RALINK_SYSCFG1 = %x\n", RALINK_SYSCFG1); ++ printk("RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); ++ printk("RALINK_CLKCFG1 = %x\n", RALINK_CLKCFG1); ++ printk("RALINK_PCIE_CLK_GEN= %x\n", RALINK_PCIE_CLK_GEN); ++ printk("RALINK_PCIE_CLK_GEN1= %x\n", RALINK_PCIE_CLK_GEN1); ++ printk("**************************\n"); ++#endif ++ ++#ifdef CONFIG_PCI_ONLY ++//PCI host only, 330T ++ RALINK_GPIOMODE = ((RALINK_GPIOMODE & (~(0x3800))) | PCI_SLOTx2); ++ RALINK_SYSCFG1 = (RALINK_SYSCFG1 | RALINK_PCI_HOST_MODE_EN | RALINK_PCIE_RC_MODE_EN); ++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST); ++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE_CLK_EN); ++#elif defined (CONFIG_PCIE_ONLY) ++//PCIe RC only, 220T ++ RALINK_SYSCFG1 = (RALINK_SYSCFG1 | RALINK_PCIE_RC_MODE_EN | RALINK_PCI_HOST_MODE_EN); ++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCI_RST); ++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCI_CLK_EN); ++#elif defined (CONFIG_PCIE_PCI_CONCURRENT) ++//PCIe PCI co-exist ++ RALINK_GPIOMODE = ((RALINK_GPIOMODE & ~(0x3800)) | PCI_SLOTx2); ++ RALINK_SYSCFG1 = (RALINK_SYSCFG1 | RALINK_PCI_HOST_MODE_EN | RALINK_PCIE_RC_MODE_EN); ++#endif ++ mdelay(500); ++ ++#if 0 ++ printk("after\n"); ++ printk("RALINK_GPIOMODE = %x\n", RALINK_GPIOMODE); ++ printk("RALINK_SYSCFG1 = %x\n", RALINK_SYSCFG1); ++ printk("RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL); ++ printk("RALINK_CLKCFG1 = %x\n", RALINK_CLKCFG1); ++ printk("RALINK_PCIE_CLK_GEN= %x\n", RALINK_PCIE_CLK_GEN); ++ printk("RALINK_PCIE_CLK_GEN1= %x\n", RALINK_PCIE_CLK_GEN1); ++ printk("**************************\n"); ++#endif ++#endif ++ ++#ifdef CONFIG_RALINK_RT2880 ++ //pci_probe_only = 1; ++ RALINK_PCI_PCICFG_ADDR = 0; ++#elif defined (CONFIG_RALINK_RT2883) ++ RALINK_PCI_PCICFG_ADDR = 0; ++#elif defined (CONFIG_RALINK_RT3883) ++ ++#ifdef CONFIG_PCIE_ONLY ++ RALINK_PCI_PCICFG_ADDR = 0; ++ //RALINK_PCI_PCICFG_ADDR |= (1<<16); ++#elif defined (CONFIG_PCI_ONLY) ++ RALINK_PCI_PCICFG_ADDR = 0; ++ RALINK_PCI_PCICFG_ADDR |= (1<<16); ++#elif defined (CONFIG_PCIE_PCI_CONCURRENT) ++ RALINK_PCI_PCICFG_ADDR = 0; ++ RALINK_PCI_PCICFG_ADDR |= (1<<16); ++#endif ++#elif defined(CONFIG_RALINK_RT6855) ++ //RALINK_PCI_PCICFG_ADDR = 0; ++ //RALINK_PCI_PCICFG_ADDR |= (1<<20); //DEV0 = 0; DEV1 = 1 ++ printk("start PCIe register access\n"); ++ RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST ++ //printk("RALINK_PCI_PCICFG_ADDR= %x\n", RALINK_PCI_PCICFG_ADDR); ++ //RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE1_RST); ++ //printk("RALINK_RSTCTRL= %x\n", RALINK_RSTCTRL); ++#elif defined(CONFIG_RALINK_RT6855A) ++ printk("start PCIe register access\n"); ++#if defined(CONFIG_RT6855A_PCIE_PORT0_ENABLE) ++ //PCI Control Register: Port1(bit22) disable ++ *((unsigned long *)(0xbfb00088)) &= ~(1<<22); ++ mdelay(1); ++ //assert PCIe RC1 reset signal ++ *((unsigned long *)(0xbfb00834)) |= ( 1<<27 ); ++ //disable reference clock of dev1 ++ *((unsigned long *)(0xbfb00090)) &= ~( 1<<3 ); ++ printk("0xbfb00834 = %x\n", *((unsigned long *)(0xbfb00834))); ++ printk("0xbfb00088 = %x\n", *((unsigned long *)(0xbfb00088))); ++ ++ ++#elif defined(CONFIG_RT6855A_PCIE_PORT01_ENABLE) ++#endif ++ //PCIe Configuration and Status Register:PCIeRST ++ RALINK_PCI_PCICFG_ADDR &= ~(1<<1); ++#if 0 ++ mdelay(500); ++ //for FPGA only ++ //port0 ++ *((unsigned long *)(0xbfbc0028)) = 0x60068880; ++ *((unsigned long *)(0xbfbc0004)) = 0x08000002; ++ *((unsigned long *)(0xbfbc0008)) = 0x00000700; ++ *((unsigned long *)(0xbfbc0000)) = 0x00160106; ++ //port1 ++ *((unsigned long *)(0xbfbc0028)) = 0x80068880; ++ *((unsigned long *)(0xbfbc0004)) = 0x08000002; ++ *((unsigned long *)(0xbfbc0008)) = 0x00000700; ++ *((unsigned long *)(0xbfbc0000)) = 0x00160106; ++#endif ++#endif ++ mdelay(500); ++ ++ //printk("RALINK_PCI_PCICFG_ADDR = %x\n", RALINK_PCI_PCICFG_ADDR); ++ ++#ifdef CONFIG_RALINK_RT3883 ++ printk("\n*************** Ralink PCIe RC mode *************\n"); ++ mdelay(500); ++ if(RALINK_SYSCFG1 & RALINK_PCIE_RC_MODE_EN){ ++ if(( RALINK_PCI1_STATUS & 0x1) == 0) ++ { ++ printk(" RALINK_PCI1_STATUS = %x\n", RALINK_PCI1_STATUS ); ++ for(i=0;i<16;i++){ ++ read_config(0, 1, 0, i<<2, &val); ++ printk("pci-to-pci 0x%02x = %08x\n", i<<2, (int)val); ++ } ++#ifdef CONFIG_PCIE_ONLY ++ printk("reset PCIe and turn off PCIe clock\n"); ++ RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST); ++ RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST); ++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE_CLK_EN); ++ printk("RALINK_CLKCFG1 = %x\n", RALINK_CLKCFG1); ++ //cgrstb, cgpdb, pexdrven0, pexdrven1, cgpllrstb, cgpllpdb, pexclken ++ RALINK_PCIE_CLK_GEN &= 0x0fff3f7f; ++ printk("RALINK_PCIE_CLK_GEN= %x\n", RALINK_PCIE_CLK_GEN); ++ return 0; ++#else ++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE_CLK_EN); ++#endif ++ } ++ } ++ if(RALINK_SYSCFG1 & RALINK_PCI_HOST_MODE_EN){ ++ RALINK_PCI_ARBCTL = 0x79; ++ } ++ ++#elif defined(CONFIG_RALINK_RT6855) ++ printk("\n*************** RT6855 PCIe RC mode *************\n"); ++ mdelay(500); ++ if(( RALINK_PCI0_STATUS & 0x1) == 0) ++ { ++ //RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE0_RST); ++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN); ++ printk("PCIE0 no card, disable it(RST&CLK)\n"); ++ pcie0_disable=1; ++ } ++ if(( RALINK_PCI1_STATUS & 0x1) == 0) ++ { ++ //RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE1_RST); ++ RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN); ++ printk("PCIE1 no card, disable it(RST&CLK)\n"); ++ pcie1_disable=1; ++ }else{ ++ if(pcie0_disable==1){ ++ /* pcie0 no card, pcie1 has card */ ++ //James want to go back, next two line ++ //RALINK_PCI_PCICFG_ADDR &= ~(0xff<<16); ++ //RALINK_PCI_PCICFG_ADDR |= 1<<16; ++ //printk("***RALINK_PCI_PCICFG_ADDR= %x\n", RALINK_PCI_PCICFG_ADDR); ++ } ++ } ++#elif defined (CONFIG_RALINK_RT6855A) ++ printk("\n*************** RT6855A PCIe RC mode *************\n"); ++ mdelay(500); ++ if(( RALINK_PCI0_STATUS & 0x1) == 0) ++ { ++ //assert PCIe RC0 reset signal ++ //*((unsigned long *)(0xbfb00834)) |= ( 1<<26 ); ++ *((unsigned long *)(0xbfb00088)) &= ~( 1<<23 ); ++ printk("PCIE0 no card, disable it\n"); ++ pcie0_disable=1; ++ } ++ if(( RALINK_PCI1_STATUS & 0x1) == 0) ++ { ++ //PCI Control Register: Port1(bit22) disable ++ *((unsigned long *)(0xbfb00088)) &= ~(1<<22); ++ mdelay(1); ++ //assert PCIe RC1 reset signal ++ *((unsigned long *)(0xbfb00834)) |= ( 1<<27 ); ++ mdelay(1); ++ //disable reference clock of dev1 ++ *((unsigned long *)(0xbfb00090)) &= ~( 1<<3 ); ++ printk("PCIE1 no card, disable it(RST&CLK)\n"); ++ pcie1_disable=1; ++ }else{ ++ if(pcie0_disable==1){ ++ /* pcie0 no card, pcie1 has card */ ++ RALINK_PCI_PCICFG_ADDR &= ~(0xff<<16); ++ RALINK_PCI_PCICFG_ADDR |= 1<<16; ++ printk("***RALINK_PCI_PCICFG_ADDR= %x\n", RALINK_PCI_PCICFG_ADDR); ++ } ++ } ++#if 0 ++ printk("\n*************** RT6855A PCIe RC mode *************\n"); ++ mdelay(1000); ++#if defined(CONFIG_RT6855A_PCIE_PORT0_ENABLE) ++ if((RALINK_PCI0_STATUS & 0x1)==0){ ++ printk("PCIE0 no card\n"); ++ return 0; ++ } ++#elif defined(CONFIG_RT6855A_PCIE_PORT01_ENABLE) ++ if((RALINK_PCI0_STATUS & 0x1)==0){ ++ printk("PCIE0 no card\n"); ++ }else{ ++ printk("PCIE0 card detected\n"); ++ } ++ if((RALINK_PCI1_STATUS & 0x1)==0){ ++ printk("PCIE1 no card\n"); ++ }else{ ++ printk("PCIE1 card detected\n"); ++ } ++ if(((RALINK_PCI0_STATUS & 0x1)==0) && ((RALINK_PCI1_STATUS & 0x1)==0)){ ++ printk("PCIE0&1 both no card\n"); ++ return 0; ++ } ++#endif ++#endif ++#elif defined (CONFIG_RALINK_RT2883) ++ printk("\n*************** Ralink PCIe RC mode *************\n"); ++ mdelay(500); ++ if(( RALINK_PCI_STATUS & 0x1) == 0) ++ { ++ printk(" RALINK_PCI_STATUS = %x\n", RALINK_PCI_STATUS ); ++ printk("************No PCIE device**********\n"); ++ for(i=0;i<16;i++){ ++ read_config(0, 0, 0, i<<2, &val); ++ printk("pci-to-pci 0x%02x = %08x\n", i<<2, val); ++ } ++ return 0; ++ } ++#else ++ for(i=0;i<0xfffff;i++); ++ RALINK_PCI_ARBCTL = 0x79; ++#endif ++ //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL); ++ ++/* ++ ioport_resource.start = rt2880_res_pci_io1.start; ++ ioport_resource.end = rt2880_res_pci_io1.end; ++*/ ++ ++ RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE; ++ RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE; ++ ++#ifdef CONFIG_RALINK_RT2880 ++ RALINK_PCI_BAR0SETUP_ADDR = 0x07FF0000; //open 1FF:32M; DISABLE ++ RALINK_PCI_IMBASEBAR0_ADDR = MEMORY_BASE; ++ RALINK_PCI_ID = 0x08021814; ++ RALINK_PCI_CLASS = 0x00800001; ++ RALINK_PCI_SUBID = 0x28801814; ++#elif defined (CONFIG_RALINK_RT2883) ++ RALINK_PCI_BAR0SETUP_ADDR = 0x01FF0000; //open 1FF:32M; DISABLE ++ RALINK_PCI_IMBASEBAR0_ADDR = MEMORY_BASE; ++ RALINK_PCI_ID = 0x08021814; ++ RALINK_PCI_CLASS = 0x06040001; ++ RALINK_PCI_SUBID = 0x28801814; ++#elif defined (CONFIG_RALINK_RT3883) ++ //PCI ++ RALINK_PCI0_BAR0SETUP_ADDR = 0x03FF0000; //open 3FF:64M; DISABLE ++ RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE; ++ RALINK_PCI0_ID = 0x08021814; ++ RALINK_PCI0_CLASS = 0x00800001; ++ RALINK_PCI0_SUBID = 0x28801814; ++ //PCIe ++ RALINK_PCI1_BAR0SETUP_ADDR = 0x03FF0000; //open 3FF:64M; DISABLE ++ RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE; ++ RALINK_PCI1_ID = 0x08021814; ++ RALINK_PCI1_CLASS = 0x06040001; ++ RALINK_PCI1_SUBID = 0x28801814; ++#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) ++ //PCIe0 ++ //if(pcie0_disable!=1){ ++ RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G ++ RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE; ++ RALINK_PCI0_ID = 0x08021814; ++ RALINK_PCI0_CLASS = 0x06040001; ++ RALINK_PCI0_SUBID = 0x28801814; ++ //} ++ //PCIe1 ++ //if(pcie1_disable!=1){ ++ RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G ++ RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE; ++ RALINK_PCI1_ID = 0x08021814; ++ RALINK_PCI1_CLASS = 0x06040001; ++ RALINK_PCI1_SUBID = 0x28801814; ++ //} ++#endif ++ ++ ++#ifdef CONFIG_RALINK_RT3883 ++ RALINK_PCI_PCIMSK_ADDR = 0x001c0000; // enable pcie/pci interrupt ++#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) ++ //if(pcie0_disable!=1){ ++ RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie0 interrupt ++ //} ++ //if(pcie1_disable!=1){ ++ RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt ++ //} ++#else ++ RALINK_PCI_PCIMSK_ADDR = 0x000c0000; // enable pci interrupt ++#endif ++ ++#ifdef CONFIG_RALINK_RT3883 ++ //PCIe ++ read_config(0, 1, 0, 0x4, &val); ++ write_config(0, 1, 0, 0x4, val|0x7); ++ //PCI ++ read_config(0, 0, 0, 0x4, &val); ++ write_config(0, 0, 0, 0x4, val|0x7); ++#elif defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) ++ //PCIe0 ++ if(pcie0_disable==0 || pcie1_disable==0){ ++ read_config(0, 0, 0, 0x4, &val); ++ write_config(0, 0, 0, 0x4, val|0x7); ++ //printk("%s %s %d\n", __FILE__, __FUNCTION__, __LINE__); ++ } ++ //PCIe1 ++ if(pcie0_disable==0 && pcie1_disable==0){ ++ read_config(0, 1, 0, 0x4, &val); ++ write_config(0, 1, 0, 0x4, val|0x7); ++ //printk("%s %s %d\n", __FILE__, __FUNCTION__, __LINE__); ++ } ++#elif defined (CONFIG_RALINK_RT2883) ++ read_config(0, 0, 0, 0x4, &val); ++ write_config(0, 0, 0, 0x4, val|0x7); ++ //FIXME ++ ////write_config(0, 0, 0, 0x18, 0x10100); ++ //write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ //read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val); ++ ////printk("BAR0 at slot 0 = %x\n", val); ++#else ++ write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); ++ read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val); ++ printk("BAR0 at slot 0 = %x\n", val); ++#endif ++#if 0 /*CONFIG_RALINK_RT6855*/ ++ ++ for(i=0;i<16;i++){ ++ read_config(0, 0, 0, i<<2, &val); ++ printk("PCI-to-PCI bridge0 0x%02x = %08x\n", i<<2, (unsigned int)val); ++ } ++ for(i=0;i<16;i++){ ++ read_config(0, 1, 0, i<<2, &val); ++ printk("PCI-to-PCI bridge1 0x%02x = %08x\n", i<<2, (unsigned int)val); ++ } ++#endif ++ register_pci_controller(&rt2880_controller); ++ return 0; ++ ++} ++#ifndef CONFIG_PCIE_PCI_NONE ++arch_initcall(init_ralink_pci); ++#endif ++ ++/* Do platform specific device initialization at pci_enable_device() time */ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ pci_cache_line_size = 32 >> 2; ++ return 0; ++} ++ ++struct pci_fixup pcibios_fixups[] = { ++// {PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources }, ++ {0} ++}; ++//DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources) ++#endif /* CONFIG_PCI */ +diff --git a/arch/mips/ralink/rt_mmap.h b/arch/mips/ralink/rt_mmap.h +new file mode 100644 +index 000000000000..3f72bb1b3879 +--- /dev/null ++++ b/arch/mips/ralink/rt_mmap.h +@@ -0,0 +1,551 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * register definition for Ralink RT-series SoC ++ * ++ * Copyright 2007 Ralink Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#ifndef __RALINK_MMAP__ ++#define __RALINK_MMAP__ ++ ++#if defined (CONFIG_RALINK_RT2880_SHUTTLE) ++ ++#define RALINK_SYSCTL_BASE 0xA0300000 ++#define RALINK_TIMER_BASE 0xA0300100 ++#define RALINK_INTCL_BASE 0xA0300200 ++#define RALINK_MEMCTRL_BASE 0xA0300300 ++#define RALINK_UART_BASE 0xA0300500 ++#define RALINK_PIO_BASE 0xA0300600 ++#define RALINK_I2C_BASE 0xA0300900 ++#define RALINK_SPI_BASE 0xA0300B00 ++#define RALINK_UART_LITE_BASE 0xA0300C00 ++#define RALINK_FRAME_ENGINE_BASE 0xA0310000 ++#define RALINK_EMBEDD_ROM_BASE 0xA0400000 ++#define RALINK_PCI_BASE 0xA0500000 ++#define RALINK_11N_MAC_BASE 0xA0600000 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_TIMER0 (1<<0) ++#define RALINK_INTCTL_WDTIMER (1<<1) ++#define RALINK_INTCTL_UART (1<<2) ++#define RALINK_INTCTL_PIO (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UARTLITE (1<<8) ++#define RALINK_INTCTL_ILL_ACCESS (1<<23) ++ ++//Reset Control Register ++#define RALINK_TIMER_RST (1<<1) ++#define RALINK_INTC_RST (1<<2) ++#define RALINK_MC_RST (1<<3) ++#define RALINK_CPU_RST (1<<4) ++#define RALINK_UART_RST (1<<5) ++#define RALINK_PIO_RST (1<<6) ++#define RALINK_I2C_RST (1<<9) ++#define RALINK_SPI_RST (1<<11) ++#define RALINK_UART2_RST (1<<12) ++#define RALINK_PCI_RST (1<<16) ++#define RALINK_2860_RST (1<<17) ++#define RALINK_FE_RST (1<<18) ++#define RALINK_PCM_RST (1<<19) ++ ++ ++#elif defined (CONFIG_RALINK_RT2880_MP) ++ ++#define RALINK_SYSCTL_BASE 0xA0300000 ++#define RALINK_TIMER_BASE 0xA0300100 ++#define RALINK_INTCL_BASE 0xA0300200 ++#define RALINK_MEMCTRL_BASE 0xA0300300 ++#define RALINK_UART_BASE 0xA0300500 ++#define RALINK_PIO_BASE 0xA0300600 ++#define RALINK_I2C_BASE 0xA0300900 ++#define RALINK_SPI_BASE 0xA0300B00 ++#define RALINK_UART_LITE_BASE 0x00300C00 ++#define RALINK_FRAME_ENGINE_BASE 0xA0400000 ++#define RALINK_EMBEDD_ROM_BASE 0xA0410000 ++#define RALINK_PCI_BASE 0xA0440000 ++#define RALINK_11N_MAC_BASE 0xA0480000 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_TIMER0 (1<<0) ++#define RALINK_INTCTL_WDTIMER (1<<1) ++#define RALINK_INTCTL_UART (1<<2) ++#define RALINK_INTCTL_PIO (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UARTLITE (1<<8) ++#define RALINK_INTCTL_ILL_ACCESS (1<<23) ++ ++//Reset Control Register ++#define RALINK_TIMER_RST (1<<1) ++#define RALINK_INTC_RST (1<<2) ++#define RALINK_MC_RST (1<<3) ++#define RALINK_CPU_RST (1<<4) ++#define RALINK_UART_RST (1<<5) ++#define RALINK_PIO_RST (1<<6) ++#define RALINK_I2C_RST (1<<9) ++#define RALINK_SPI_RST (1<<11) ++#define RALINK_UART2_RST (1<<12) ++#define RALINK_PCI_RST (1<<16) ++#define RALINK_2860_RST (1<<17) ++#define RALINK_FE_RST (1<<18) ++#define RALINK_PCM_RST (1<<19) ++ ++#elif defined (CONFIG_RALINK_RT3052) ++ ++#define RALINK_SYSCTL_BASE 0xB0000000 ++#define RALINK_TIMER_BASE 0xB0000100 ++#define RALINK_INTCL_BASE 0xB0000200 ++#define RALINK_MEMCTRL_BASE 0xB0000300 ++#define RALINK_PCM_BASE 0xB0000400 ++#define RALINK_UART_BASE 0x10000500 ++#define RALINK_PIO_BASE 0xB0000600 ++#define RALINK_GDMA_BASE 0xB0000700 ++#define RALINK_NAND_CTRL_BASE 0xB0000800 ++#define RALINK_I2C_BASE 0xB0000900 ++#define RALINK_I2S_BASE 0xB0000A00 ++#define RALINK_SPI_BASE 0xB0000B00 ++#define RALINK_UART_LITE_BASE 0x10000C00 ++#define RALINK_FRAME_ENGINE_BASE 0xB0100000 ++#define RALINK_ETH_SW_BASE 0xB0110000 ++#define RALINK_11N_MAC_BASE 0xB0180000 ++#define RALINK_USB_OTG_BASE 0x101C0000 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_SYSCTL (1<<0) ++#define RALINK_INTCTL_TIMER0 (1<<1) ++#define RALINK_INTCTL_WDTIMER (1<<2) ++#define RALINK_INTCTL_ILL_ACCESS (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UART (1<<5) ++#define RALINK_INTCTL_PIO (1<<6) ++#define RALINK_INTCTL_DMA (1<<7) ++#define RALINK_INTCTL_NAND (1<<8) ++#define RALINK_INTCTL_PC (1<<9) ++#define RALINK_INTCTL_I2S (1<<10) ++#define RALINK_INTCTL_UARTLITE (1<<12) ++#define RALINK_INTCTL_ESW (1<<17) ++#define RALINK_INTCTL_OTG (1<<18) ++#define RALINK_INTCTL_OTG_IRQN 18 ++#define RALINK_INTCTL_GLOBAL (1<<31) ++ ++//Reset Control Register ++#define RALINK_SYS_RST (1<<0) ++#define RALINK_CPU_RST (1<<1) ++#define RALINK_TIMER_RST (1<<8) ++#define RALINK_INTC_RST (1<<9) ++#define RALINK_MC_RST (1<<10) ++#define RALINK_PCM_RST (1<<11) ++#define RALINK_UART_RST (1<<12) ++#define RALINK_PIO_RST (1<<13) ++#define RALINK_DMA_RST (1<<14) ++#define RALINK_I2C_RST (1<<16) ++#define RALINK_I2S_RST (1<<17) ++#define RALINK_SPI_RST (1<<18) ++#define RALINK_UARTL_RST (1<<19) ++#define RALINK_RT2872_RST (1<<20) ++#define RALINK_FE_RST (1<<21) ++#define RALINK_OTG_RST (1<<22) ++#define RALINK_SW_RST (1<<23) ++#define RALINK_EPHY_RST (1<<24) ++ ++#elif defined (CONFIG_RALINK_RT3352) ++ ++#define RALINK_SYSCTL_BASE 0xB0000000 ++#define RALINK_TIMER_BASE 0xB0000100 ++#define RALINK_INTCL_BASE 0xB0000200 ++#define RALINK_MEMCTRL_BASE 0xB0000300 ++#define RALINK_UART_BASE 0x10000500 ++#define RALINK_PIO_BASE 0xB0000600 ++#define RALINK_I2C_BASE 0xB0000900 ++#define RALINK_I2S_BASE 0xB0000A00 ++#define RALINK_SPI_BASE 0xB0000B00 ++#define RALINK_NAND_CTRL_BASE 0xB0000800 ++#define RALINK_UART_LITE_BASE 0x10000C00 ++#define RALINK_PCM_BASE 0xB0002000 ++#define RALINK_GDMA_BASE 0xB0002800 ++#define RALINK_FRAME_ENGINE_BASE 0xB0100000 ++#define RALINK_ETH_SW_BASE 0xB0110000 ++#define RALINK_USB_DEV_BASE 0x10120000 ++#define RALINK_11N_MAC_BASE 0xB0180000 ++#define RALINK_USB_HOST_BASE 0x101C0000 ++ ++#define RALINK_MCNT_CFG 0xB0000D00 ++#define RALINK_COMPARE 0xB0000D04 ++#define RALINK_COUNT 0xB0000D08 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_SYSCTL (1<<0) ++#define RALINK_INTCTL_TIMER0 (1<<1) ++#define RALINK_INTCTL_WDTIMER (1<<2) ++#define RALINK_INTCTL_ILL_ACCESS (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UART (1<<5) ++#define RALINK_INTCTL_PIO (1<<6) ++#define RALINK_INTCTL_DMA (1<<7) ++#define RALINK_INTCTL_PC (1<<9) ++#define RALINK_INTCTL_I2S (1<<10) ++#define RALINK_INTCTL_UARTLITE (1<<12) ++#define RALINK_INTCTL_ESW (1<<17) ++#define RALINK_INTCTL_OTG (1<<18) ++#define RALINK_INTCTL_GLOBAL (1<<31) ++ ++//Reset Control Register ++#define RALINK_SYS_RST (1<<0) ++#define RALINK_TIMER_RST (1<<8) ++#define RALINK_INTC_RST (1<<9) ++#define RALINK_MC_RST (1<<10) ++#define RALINK_PCM_RST (1<<11) ++#define RALINK_UART_RST (1<<12) ++#define RALINK_PIO_RST (1<<13) ++#define RALINK_DMA_RST (1<<14) ++#define RALINK_I2C_RST (1<<16) ++#define RALINK_I2S_RST (1<<17) ++#define RALINK_SPI_RST (1<<18) ++#define RALINK_UARTL_RST (1<<19) ++#define RALINK_WLAN_RST (1<<20) ++#define RALINK_FE_RST (1<<21) ++#define RALINK_UHST_RST (1<<22) ++#define RALINK_ESW_RST (1<<23) ++#define RALINK_EPHY_RST (1<<24) ++#define RALINK_UDEV_RST (1<<25) ++ ++ ++//Clock Conf Register ++#define RALINK_UPHY1_CLK_EN (1<<20) ++#define RALINK_UPHY0_CLK_EN (1<<18) ++#define RALINK_GE1_CLK_EN (1<<16) ++ ++ ++#elif defined (CONFIG_RALINK_RT5350) ++ ++#define RALINK_SYSCTL_BASE 0xB0000000 ++#define RALINK_TIMER_BASE 0xB0000100 ++#define RALINK_INTCL_BASE 0xB0000200 ++#define RALINK_MEMCTRL_BASE 0xB0000300 ++#define RALINK_UART_BASE 0x10000500 ++#define RALINK_PIO_BASE 0xB0000600 ++#define RALINK_I2C_BASE 0xB0000900 ++#define RALINK_I2S_BASE 0xB0000A00 ++#define RALINK_SPI_BASE 0xB0000B00 ++#define RALINK_UART_LITE_BASE 0x10000C00 ++#define RALINK_PCM_BASE 0xB0002000 ++#define RALINK_GDMA_BASE 0xB0002800 ++#define RALINK_FRAME_ENGINE_BASE 0xB0100000 ++#define RALINK_ETH_SW_BASE 0xB0110000 ++#define RALINK_USB_DEV_BASE 0x10120000 ++#define RALINK_11N_MAC_BASE 0xB0180000 ++#define RALINK_USB_HOST_BASE 0x101C0000 ++ ++#define RALINK_MCNT_CFG 0xB0000D00 ++#define RALINK_COMPARE 0xB0000D04 ++#define RALINK_COUNT 0xB0000D08 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_SYSCTL (1<<0) ++#define RALINK_INTCTL_TIMER0 (1<<1) ++#define RALINK_INTCTL_WDTIMER (1<<2) ++#define RALINK_INTCTL_ILL_ACCESS (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UART (1<<5) ++#define RALINK_INTCTL_PIO (1<<6) ++#define RALINK_INTCTL_DMA (1<<7) ++#define RALINK_INTCTL_PC (1<<9) ++#define RALINK_INTCTL_I2S (1<<10) ++#define RALINK_INTCTL_UARTLITE (1<<12) ++#define RALINK_INTCTL_ESW (1<<17) ++#define RALINK_INTCTL_USB_HOST (1<<18) ++#define RALINK_INTCTL_USB_DEV (1<<19) ++#define RALINK_INTCTL_GLOBAL (1<<31) ++ ++//Reset Control Register ++#define RALINK_SYS_RST (1<<0) ++#define RALINK_TIMER_RST (1<<8) ++#define RALINK_INTC_RST (1<<9) ++#define RALINK_MC_RST (1<<10) ++#define RALINK_PCM_RST (1<<11) ++#define RALINK_UART_RST (1<<12) ++#define RALINK_PIO_RST (1<<13) ++#define RALINK_DMA_RST (1<<14) ++#define RALINK_I2C_RST (1<<16) ++#define RALINK_I2S_RST (1<<17) ++#define RALINK_SPI_RST (1<<18) ++#define RALINK_UARTL_RST (1<<19) ++#define RALINK_WLAN_RST (1<<20) ++#define RALINK_FE_RST (1<<21) ++#define RALINK_UHST_RST (1<<22) ++#define RALINK_ESW_RST (1<<23) ++#define RALINK_EPHY_RST (1<<24) ++#define RALINK_UDEV_RST (1<<25) ++#define RALINK_MIPSC_RST (1<<28) ++ ++//Clock Conf Register ++#define RALINK_UPHY0_CLK_EN (1<<18) ++#define RALINK_GE1_CLK_EN (1<<16) ++ ++#elif defined (CONFIG_RALINK_RT2883) ++ ++#define RALINK_SYSCTL_BASE 0xB0000000 ++#define RALINK_TIMER_BASE 0xB0000100 ++#define RALINK_INTCL_BASE 0xB0000200 ++#define RALINK_MEMCTRL_BASE 0xB0000300 ++#define RALINK_PCM_BASE 0xB0000400 ++#define RALINK_UART_BASE 0x10000500 ++#define RALINK_PIO_BASE 0xB0000600 ++#define RALINK_GDMA_BASE 0xB0000700 ++#define RALINK_NAND_CTRL_BASE 0xB0000800 ++#define RALINK_I2C_BASE 0xB0000900 ++#define RALINK_I2S_BASE 0xB0000A00 ++#define RALINK_SPI_BASE 0xB0000B00 ++#define RALINK_UART_LITE_BASE 0x10000C00 ++#define RALINK_FRAME_ENGINE_BASE 0xB0100000 ++#define RALINK_PCI_BASE 0xB0140000 ++#define RALINK_11N_MAC_BASE 0xB0180000 ++#define RALINK_USB_OTG_BASE 0x101C0000 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_SYSCTL (1<<0) ++#define RALINK_INTCTL_TIMER0 (1<<1) ++#define RALINK_INTCTL_WDTIMER (1<<2) ++#define RALINK_INTCTL_ILL_ACCESS (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UART (1<<5) ++#define RALINK_INTCTL_PIO (1<<6) ++#define RALINK_INTCTL_DMA (1<<7) ++#define RALINK_INTCTL_NAND (1<<8) ++#define RALINK_INTCTL_PC (1<<9) ++#define RALINK_INTCTL_I2S (1<<10) ++#define RALINK_INTCTL_UARTLITE (1<<12) ++#define RALINK_INTCTL_OTG (1<<18) ++#define RALINK_INTCTL_OTG_IRQN 18 ++#define RALINK_INTCTL_GLOBAL (1<<31) ++ ++//Reset Control Register ++#define RALINK_SYS_RST (1<<0) ++#define RALINK_CPU_RST (1<<1) ++#define RALINK_TIMER_RST (1<<8) ++#define RALINK_INTC_RST (1<<9) ++#define RALINK_MC_RST (1<<10) ++#define RALINK_PCM_RST (1<<11) ++#define RALINK_UART_RST (1<<12) ++#define RALINK_PIO_RST (1<<13) ++#define RALINK_DMA_RST (1<<14) ++#define RALINK_I2C_RST (1<<16) ++#define RALINK_I2S_RST (1<<17) ++#define RALINK_SPI_RST (1<<18) ++#define RALINK_UARTL_RST (1<<19) ++#define RALINK_WLAN_RST (1<<20) ++#define RALINK_FE_RST (1<<21) ++#define RALINK_OTG_RST (1<<22) ++#define RALINK_PCIE_RST (1<<23) ++ ++#elif defined (CONFIG_RALINK_RT3883) ++ ++#define RALINK_SYSCTL_BASE 0xB0000000 ++#define RALINK_TIMER_BASE 0xB0000100 ++#define RALINK_INTCL_BASE 0xB0000200 ++#define RALINK_MEMCTRL_BASE 0xB0000300 ++#define RALINK_UART_BASE 0x10000500 ++#define RALINK_PIO_BASE 0xB0000600 ++#define RALINK_NOR_CTRL_BASE 0xB0000700 ++#define RALINK_NAND_CTRL_BASE 0xB0000810 ++#define RALINK_I2C_BASE 0xB0000900 ++#define RALINK_I2S_BASE 0xB0000A00 ++#define RALINK_SPI_BASE 0xB0000B00 ++#define RALINK_UART_LITE_BASE 0x10000C00 ++#define RALINK_PCM_BASE 0xB0002000 ++#define RALINK_GDMA_BASE 0xB0002800 ++#define RALINK_CODEC1_BASE 0xB0003000 ++#define RALINK_CODEC2_BASE 0xB0003800 ++#define RALINK_FRAME_ENGINE_BASE 0xB0100000 ++#define RALINK_USB_DEV_BASE 0x10120000 ++#define RALINK_PCI_BASE 0xB0140000 ++#define RALINK_11N_MAC_BASE 0xB0180000 ++#define RALINK_USB_HOST_BASE 0x101C0000 ++#define RALINK_PCIE_BASE 0xB0200000 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_SYSCTL (1<<0) ++#define RALINK_INTCTL_TIMER0 (1<<1) ++#define RALINK_INTCTL_WDTIMER (1<<2) ++#define RALINK_INTCTL_ILL_ACCESS (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UART (1<<5) ++#define RALINK_INTCTL_PIO (1<<6) ++#define RALINK_INTCTL_DMA (1<<7) ++#define RALINK_INTCTL_NAND (1<<8) ++#define RALINK_INTCTL_PC (1<<9) ++#define RALINK_INTCTL_I2S (1<<10) ++#define RALINK_INTCTL_UARTLITE (1<<12) ++#define RALINK_INTCTL_UHST (1<<18) ++#define RALINK_INTCTL_UDEV (1<<19) ++ ++//Reset Control Register ++#define RALINK_SYS_RST (1<<0) ++#define RALINK_TIMER_RST (1<<8) ++#define RALINK_INTC_RST (1<<9) ++#define RALINK_MC_RST (1<<10) ++#define RALINK_PCM_RST (1<<11) ++#define RALINK_UART_RST (1<<12) ++#define RALINK_PIO_RST (1<<13) ++#define RALINK_DMA_RST (1<<14) ++#define RALINK_NAND_RST (1<<15) ++#define RALINK_I2C_RST (1<<16) ++#define RALINK_I2S_RST (1<<17) ++#define RALINK_SPI_RST (1<<18) ++#define RALINK_UARTL_RST (1<<19) ++#define RALINK_WLAN_RST (1<<20) ++#define RALINK_FE_RST (1<<21) ++#define RALINK_UHST_RST (1<<22) ++#define RALINK_PCIE_RST (1<<23) ++#define RALINK_PCI_RST (1<<24) ++#define RALINK_UDEV_RST (1<<25) ++#define RALINK_FLASH_RST (1<<26) ++ ++//Clock Conf Register ++#define RALINK_UPHY1_CLK_EN (1<<20) ++#define RALINK_UPHY0_CLK_EN (1<<18) ++#define RALINK_GE1_CLK_EN (1<<16) ++ ++#elif defined (CONFIG_RALINK_RT6855) ++ ++#define RALINK_SYSCTL_BASE 0xB0000000 ++#define RALINK_TIMER_BASE 0xB0000100 ++#define RALINK_INTCL_BASE 0xB0000200 ++#define RALINK_MEMCTRL_BASE 0xB0000300 ++#define RALINK_UART_BASE 0x10000500 ++#define RALINK_PIO_BASE 0xB0000600 ++#define RALINK_I2C_BASE 0xB0000900 ++#define RALINK_I2S_BASE 0xB0000A00 ++#define RALINK_SPI_BASE 0xB0000B00 ++#define RALINK_NAND_CTRL_BASE 0xB0000800 ++#define RALINK_UART_LITE_BASE 0x10000C00 ++#define RALINK_PCM_BASE 0xB0002000 ++#define RALINK_GDMA_BASE 0xB0002800 ++#define RALINK_FRAME_ENGINE_BASE 0xB0100000 ++#define RALINK_ETH_SW_BASE 0xB0110000 ++#define RALINK_PCI_BASE 0xB0140000 ++#define RALINK_USB_DEV_BASE 0x10120000 ++#define RALINK_11N_MAC_BASE 0x00000000 ++#define RALINK_USB_HOST_BASE 0x101C0000 ++ ++#define RALINK_MCNT_CFG 0xB0000D00 ++#define RALINK_COMPARE 0xB0000D04 ++#define RALINK_COUNT 0xB0000D08 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_SYSCTL (1<<0) ++#define RALINK_INTCTL_TIMER0 (1<<1) ++#define RALINK_INTCTL_WDTIMER (1<<2) ++#define RALINK_INTCTL_ILL_ACCESS (1<<3) ++#define RALINK_INTCTL_PCM (1<<4) ++#define RALINK_INTCTL_UART (1<<5) ++#define RALINK_INTCTL_PIO (1<<6) ++#define RALINK_INTCTL_DMA (1<<7) ++#define RALINK_INTCTL_PC (1<<9) ++#define RALINK_INTCTL_I2S (1<<10) ++#define RALINK_INTCTL_UARTLITE (1<<12) ++#define RALINK_INTCTL_ESW (1<<17) ++#define RALINK_INTCTL_OTG (1<<18) ++#define RALINK_INTCTL_GLOBAL (1<<31) ++ ++//Reset Control Register ++#define RALINK_SYS_RST (1<<0) ++#define RALINK_TIMER_RST (1<<8) ++#define RALINK_INTC_RST (1<<9) ++#define RALINK_MC_RST (1<<10) ++#define RALINK_PCM_RST (1<<11) ++#define RALINK_UART_RST (1<<12) ++#define RALINK_PIO_RST (1<<13) ++#define RALINK_DMA_RST (1<<14) ++#define RALINK_I2C_RST (1<<16) ++#define RALINK_I2S_RST (1<<17) ++#define RALINK_SPI_RST (1<<18) ++#define RALINK_UARTL_RST (1<<19) ++#define RALINK_FE_RST (1<<21) ++#define RALINK_UHST_RST (1<<22) ++#define RALINK_ESW_RST (1<<23) ++#define RALINK_EPHY_RST (1<<24) ++#define RALINK_UDEV_RST (1<<25) ++#define RALINK_PCIE0_RST (1<<26) ++#define RALINK_PCIE1_RST (1<<27) ++ ++//Clock Conf Register ++#define RALINK_UPHY0_CLK_EN (1<<25) ++#define RALINK_PCIE0_CLK_EN (1<<26) ++#define RALINK_PCIE1_CLK_EN (1<<27) ++ ++ ++#elif defined (CONFIG_RALINK_RT6855A) ++ ++#define RALINK_SYSCTL_BASE 0xBFB00000 ++#define RALINK_TIMER_BASE 0xBFBF0100 ++#define RALINK_INTCL_BASE 0xBFB40000 ++#define RALINK_MEMCTRL_BASE 0xBFB20000 ++#define RALINK_PIO_BASE 0xBFBF0200 ++#define RALINK_NAND_CTRL_BASE 0xBFBE0010 ++#define RALINK_I2C_BASE 0xBFBF8000 ++#define RALINK_I2S_BASE 0xBFBF8100 ++#define RALINK_SPI_BASE 0xBFBC0B00 ++#define RALINK_UART_LITE_BASE 0xBFBF0000 ++#define RALINK_UART_LITE2_BASE 0xBFBF0300 ++#define RALINK_PCM_BASE 0xBFBD0000 ++#define RALINK_GDMA_BASE 0xBFB30000 ++#define RALINK_FRAME_ENGINE_BASE 0xBFB50000 ++#define RALINK_ETH_SW_BASE 0xBFB58000 ++#define RALINK_11N_MAC_BASE 0x00000000 ++//#define RALINK_USB_DEV_BASE 0xB0120000 ++#define RALINK_CRYPTO_ENGINE_BASE 0xBFB70000 ++#define RALINK_PCI_BASE 0xBFB80000 ++//#define RALINK_USB_HOST_BASE 0xB01C0000 ++#define RALINK_PCIE_BASE 0xBFB81000 ++ ++//Interrupt Controller ++#define RALINK_INTCTL_UARTLITE (1<<0) ++#define RALINK_INTCTL_PIO (1<<10) ++#define RALINK_INTCTL_PCM (1<<11) ++#define RALINK_INTCTL_DMA (1<<14) ++#define RALINK_INTCTL_GMAC2 (1<<15) ++#define RALINK_INTCTL_PCI (1<<17) ++#define RALINK_INTCTL_UHST2 (1<<20) ++#define RALINK_INTCTL_GMAC1 (1<<21) ++#define RALINK_INTCTL_UHST1 (1<<23) ++#define RALINK_INTCTL_PCIE (1<<24) ++#define RALINK_INTCTL_NAND (1<<25) ++#define RALINK_INTCTL_SPI (1<<27) ++ ++//Reset Control Register ++#define RALINK_PCM_RST (1<<11) ++#define RALINK_DMA_RST (1<<14) ++#define RALINK_I2C_RST (1<<16) ++#define RALINK_I2S_RST (1<<2) /* IMR1 */ ++ ++//Clock Conf Register ++#define RALINK_UPHY0_CLK_EN (1<<25) ++#define RALINK_PCIE0_CLK_EN (1<<26) ++#define RALINK_PCIE1_CLK_EN (1<<27) ++ ++#endif ++#endif +-- +2.27.0 + -- 2.27.0 _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel