Hi Sander,
On 06/11/2021 20:47, Sander Vanheule wrote:
With some extra testing, I have found that the network port that was active
before a
watchdog reset, doesn't do much anymore after restarting. Replugging the cable
into a port
that was not used before the reset works, but that's not really useful if the
system isn't
readily accessible or has no unused ports. I don't think the current network
code resets
more than just the CPU NIC, so maybe the networking code could be ammended to
also reset
the switch control tables, etc. Any thoughts on this?
Resetting different SoC parts in the RTL chips is very badly documented in the
GPLed SDK code
available, in fact the SDK only ever resets the NIC itself. Combine that with
the fact that
the global SoC reset at least on the RTL8380 SoCs does not put the chip into
the same state
as a power off, we are left with experimenting. My impression is that the 838x
based
routers are not supposed to be software reset. Instead once the SoC is
configured for switching
by a user through a web interface they will run forever doing everything in
silicon even
if the CPU hangs completely.
In OWRT resets happen in rtl838x_hw_reset(), this is the latest version with
RTL93xx support:
/* Reset NIC */
if (priv->family_id == RTL9300_FAMILY_ID || priv->family_id ==
RTL9310_FAMILY_ID)
sw_w32(0x86, priv->r->rst_glb_ctrl);
else
sw_w32(0x8, priv->r->rst_glb_ctrl);
do { /* Wait for reset of NIC and Queues done */
udelay(20);
} while (sw_r32(priv->r->rst_glb_ctrl) & 0xff);
You can try to reset more parts of the switch by adding more bits to what is
written
into the RST_GLB_CTRL register. Obvious candidates in addition to bit 3 (NIC
reset) are:
BIT 0: SW_RST (switch reset?)
BIT 1: SW_CFG_RST (switch configuration reset?)
BIT 2: SW_Q_RST (switch Queues reset, this is done on the 93xx platforms in the
SDK)
BIT 3: SW_NIC_RST
BIT 4: SW_SERDES_RST (reset the built-in SerDes?)
BIT 5: SW_PHY_RST (reset the built in PHY of the RTL838x? That is what I would
try first.)
I would avoid the CPU_MEM_RST reset which sounds like a reset of the DRAM
interface.
The TBL_*_RST bits seem to allow resetting the various L2 configuration tables
but unless you see
a strange configuration after a WD trigger, I would not touch those.
Of course the issue you describe could also be due to an issue with the PHY-MAC
communication
and you need to reset the external PHY (you don't mention the specific device).
Cheers,
Birger
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