Hi Gautam, On Saturday 28 February 2015 06:48:48 mind entropy wrote: > On Sat, Feb 21, 2015 at 12:21 PM, mind entropy <mindentr...@gmail.com> wrote: > > I am trying to understand the flash access timing calculations in > > the barebox code and I have some doubts. ( I am a newbie in NAND flash > > ). > > > > In the code the comment says (in > > arch/arm/boards/friendlyarm-mini2440/config.h) > > > > /* > > * Flash access timings > > * Tacls = 0ns (but 20ns data setup time) > > * Twrph0 = 25ns (write) 35ns (read) > > * Twrph1 = 10ns (10ns data hold time) > > * Read cycle time = 50ns > > * > > * Assumed HCLK is 100MHz > > * Tacls = 1 (-> 20ns) > > * Twrph0 = 3 (-> 40ns) > > * Twrph1 = 1 (-> 20ns) > > * Cycle time = 80ns > > */ > > > > I have a K9F2G08U0B 256MB NAND flash( > > http://115.28.165.193/down/datasheet/Peripheral/NandFlash/K9F2G08x0B.pdf > > ) . I know the HCLK cycle time is 10ns. (1/100MHz). Could you please > > help me out with the calculation of Tacls,Twrph0 and Twph1? What are > > the values/timing diagrams I should look in the NAND datasheet related > > to this? > > Can somebody please give some help here.
It seems the new NAND flash is faster than the old one. So you can continue to use the older (and slower) timings. No real need to change anything. Regards, Juergen -- Pengutronix e.K. | Juergen Borleis | Industrial Linux Solutions | http://www.pengutronix.de/ |
