After searching the list about 0 delay delwrites~, I was reminded that they do indeed produce at least a one block delay. It seems send~ and receive~ do too. So, I set the abstraction to have [block 1] and that's fixed it. Hope this message helps anyone. I'll upload a new version to Github later for anyone who is looking for an audio rate shift register.
Sam On Tue, Feb 22, 2022 at 5:08 PM Samuel Burt <composer.samuel.b...@gmail.com> wrote: > Hi, all. > > I'm having a problem with an abstraction I've created to produce a shift > register at the audio rate. > > Here's a picture of the patch and a help patch explaining how it works. > > https://raw.githubusercontent.com/TricksterSam/Personal-Pure-Data-Development/main/shiftregister~.png > > Also, here's a Github link if you want to download and try it. > https://github.com/TricksterSam/Personal-Pure-Data-Development > > *Quick description:* > The abstraction shiftregister~ is an object that generates 8 random bits > set to 1 or 0 (output as signals). The bits cycle when a (gate) signal in > the left inlet decreases in value. A signal in the right inlet sets the > probability that the first bit will flip. When the right inlet is 0, the > bits will cycle unchanged. At 0.5, the cycle will be completely random. At > 1, the cycle will flip every bit creating a 16-stage sequence. > In my help patch, I distinguish the outputs by multiplying them each by > a power of two and combine them to form an 8-bit number which is then > sonified as a note sequence by the [makebeep] subpatch. > > *My problem:* > I've noticed that as I increase the cycle frequency into the kHz range, > some instabilities occur. In one instance, I've locked the cycle with a 0% > chance for a bit to flip. When I increase the frequency high enough, the > cycle will either flatten out to a single value, or I've observed the > pattern change so only one value is high while all the others are low. > In addition, if I run phasor~ at 1/8 of the cycle speed, I expect it to > see the phasor synced to the cycle from the shift register. At lower > frequencies this works fine, but at higher frequencies the phase starts > drifting. > > *How it works:* > I'm using sixteen [samphold~] objects in a loop. Odd numbered [samphold]~s > receive a gate (square wave created from a phasor) while even numbered > [samphold]~s receive an inverted gate. > Is there some kind of delay introduced by [delwrite~] [delread~] even > when the delay is set to 0ms? Is there any delay created by the [samphold~] > objects? > Maybe someone can help me make sense of this, or has a better way of > producing audio rate shift registers. Please, let me know! > > >
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