thanks Abd ul-Rahman yes it's a 3,3 volts split plane and the pad in error is 24 volts i want to say that there are may other pad like this on the board...and why this pad ? the constraint for this pad is the constraint for all pads pads parameters : hole size 0,6mm x,y 1mm multilayer plated the plane clearance is 0,3mm the plane connect is 0,254mm for expansion width and gap when routing the 24v net i use a pad to go across the card and putting this pad on net it take automatically the name of the net!! visually protel shows the pad connected to 3,3v internal plane...i can see the air-gap arround the pad it's connected on the board...i have alas determined it!!!
-----Message d'origine----- De : [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] la part de Abd ul-Rahman Lomax Envoye : mercredi 12 juillet 2006 21:14 A : Protel EDA Discussion List Objet : Re: [PEDA] pb short-circuit beetwen pad and internal plane with protel 99se At 11:37 AM 7/12/2006, d-fabbro wrote: >I'm using protel 99se and for the third time since several years i have >a serious problem >a via or pad with a label attached is abnormally connected to internal >plane!!! >DRC is ok !!! and the via or pad being discussed is not visually in >error ( color changing) Serious question: how do you know it is abnormally connected? If you look at the gerber files, can you see that it is incorrect? (note that you'll need to look at the *Holes*). And remember that holes to be plated are generally drilled oversize and then plated back to the nominal size, so the copper plating on the wall of a hole will extend beyond where Protel thinks it will be, by the thickness of the plating. Plus, of course, the allowed variation in the hole size. I assume from what you wrote that it is connected to a voltage plane. Is this a split plane? What is the net assigned to the plane and is the same net assigned to the pad or via (in which case it is correctly connected). What are the pad or via parameters and what rules have you set that might affect how it is connected? "With a label attached" is not clear to me. Do you mean a net assignment, or do you mean a pad name (vias can't be named)? Or do you mean something else? Essentially, is Protel showing this pad or via as connected to the plane? Or are you only finding it connected in the photoplots or on the board itself? Internal planes are calculated layers, they are generated from what is on other layers plus specified parameters, such as clearances, thermal reliefs, etc. So an abnormal connection typically means that you are feeding the wrong information to the photoplot routines; and, in this situation, you won't see DRC errors since Protel does not know that there is one. Mostly likely, it thinks you want to connect the pad or via to the plane. So the most common question you will need to answer is, "Why does Protel think this pad or via is to be connected? or otherwise plotted in such a way as to cause a connection?" ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected] ---------------------------------------------------------------------------- ----------- Orange vous informe que cet e-mail a ete controle par l'anti-virus mail. Aucun virus connu a ce jour par nos services n'a ete detecte. ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
