Hey Andrew,

The short answer is we don't. What I mean is that once I array paste the
individual design, I get a rats nest of net connection lines (you must
select "keep net name" under "Paste special") between the boards and I get a
bunch of Protel generated component designators. I hide the net connection
lines since the DRC passed as an individual PCB ((you did run a batch DRC
before panellizing, right?). As for the designators, unless you've selected
"duplicate designators," protel will automatically add "_x" (x being a
number) to duplicate designators so that each one is unique. 

How do we generate BOMs and PicknPlace files? The contract manufacturers
that we have worked with use the ascii pcb format to program their
PicknPlace (Our CMs are companies that we trust with such information). The
BOM is generated from the individual PCB schematic. Essentially, the CM
reads in the pcb file and then deletes all components that aren't listed on
the BOM (all those with an "_x" designator). This leaves them with a pnp
information for a single board which they array themselves. 

Once we start pasting in the individual boards, basically we ignore any rule
violations. I'm sure we could do this in Camtastic, but I'm pretty sure
you'd have trouble doing effective rule checks anyhow.

I hope that answers the question. I'm still glossing over some details since
its pretty hard to explain some of the ins and outs until someone has tried
this method. 

Darcy

-----Original Message-----
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] 
Sent: October 20, 2006 2:09 PM
To: [EMAIL PROTECTED]; [email protected]
Subject: RE: [PEDA] Generating panel of PCBs...

How do resolve the ref designator and net problems? 

>-----Original Message-----
>From: [EMAIL PROTECTED]
>[mailto:[EMAIL PROTECTED] On Behalf Of Darcy Davis
>Sent: Friday, October 20, 2006 11:04 AM
>To: PEDA
>Subject: Re: [PEDA] Generating panel of PCBs...
>
>Hey Dusan,
>
>We're working in P99SE and we panelize almost all of our designs within 
>P99SE. The reasoning for this is that we have some features on our 
>panel that are schematic based. I'm pretty sure we could combine the 
>two gerber sets in camtastic, but we've got a fairly smooth process 
>that works within P99SE.
>Essentially, we define the panel and then place an array of "PCB 
>footprint" parts in this panel to define where each individual PCB will 
>be.
>This "PCB footprint" is just the board outline, routing path and 
>mousebytes to ensure that our panel features don't interfere with any 
>of the individual board features. Once both the panel and the 
>individual board are defined, you copy and paste the individual board 
>into the panel. There are a bunch of "gotchas" when doing this, but I 
>won't go into detail unless someone asks...
>
>Darcy
>
>-----Original Message-----
>From: [EMAIL PROTECTED]
>[mailto:[EMAIL PROTECTED] On Behalf Of Dusan Mihajlovic
>Sent: October 20, 2006 1:40 AM
>To: Protel EDA Discussion List
>Subject: [PEDA] Generating panel of PCBs...
>
>Hi,
>
>in regards to previous discussion on generating panel of PCBs in P99SE 
>I would like to ask you what are your experience with this? What 
>software tools are you using to generate panel of PCBs and what are 
>your experience with manufacturer.
>
>Until now I only sent single PCBs to my manufacturer and "engineering 
>cost"
>for preparing panel of PCBs just went too high. I would like to do this 
>my self and save my company some of the charges.
>
>Thanks,
>
>Dusan
>
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