Take a look at lmbench
http://www.bitmover.com/lmbench/
This reports memory latency. You can get an estimate of the cost of TLB
handling by subtracting the cost of a cache miss where there is no TLB
miss from the cost of a cache miss where there is a TLB miss.
If you want to do this independently, then allocate a chunk of memory
and fill it with a circular linked list - use one pointer per cache
line. The tricky bit here is that you want to permute the linked list so
that hardware prefetch doesn't detect a pattern.
Then time how long it takes to iterate around the list a number of times.
If the array fits into the L1 cache, this will give you the L1 cache
latency. Similarly for the L2 etc. If it doesn't fit into cache you'll
get an estimate of memory latency. If it doesn't fit into cache and it
is too large to be mapped by the TLB (using whatever page size you
have), then it will measure the cost of a memory miss + cost of TLB miss.
I'd suggest that you also run this under cputrack to confirm the number
of cache and TLB misses you are getting.
HTH,
Darryl.
On 8/20/2010 9:33 PM, Rayson Ho wrote:
IMO, this problem is harder than "just porting trapstat to x86/x64" --
if you google trapstat+t2, or trapstat+ultrasparc+t2, you will find
that measuring the cost of TLB misses is equally hard on UltraSPARC T2
as well, as both x86/x64 and T2 support hardware table walk.
Rayson
On Sat, Aug 21, 2010 at 12:21 AM, Kishore Kumar Pusukuri
<[email protected]> wrote:
I am able to measure TLB miss-rate of a multi-threaded application running on
my multi-core AMD Opteron machine by reading performance monitoring event
counters using cpustat utility. However, I would like to measure the amount of
time spent on TLB misses? Specifically, I am looking a way like the utility
trapstat functions. Please share your ideas.
Thank you.
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Darryl Gove
Compiler Performance Engineering
Blog : http://blogs.sun.com/d/
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http://my.safaribooksonline.com/9780768681390
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