Hi,
I need to program IBS in Barcelona processors. The event I am looking for is
L2 load cache miss and I need the data addresses for such loads.
Can someone point me to some relevant documentation ?
I have a link regarding LWP profiling support of AMD but I guess it is not
yet out. Here is the link :
http://developer.amd.com/assets/HardwareExtensionsforLightweightProfilingPublic20070720.pdf
Is it significantly different from the current IBS support ?
Also, I have 2.6.23 kernel patched with perfmon. Which libpfm should I use ?
libpfm-3.3 has a sample example for IBS but I am not sure if this is the
best library with the kernel that i have. Please guide.
Sincerely,
Vivek Thakkar
Graduate Student and Research Assistant
CSC Department, NC State University
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