Nicolas, On Thu, Dec 21, 2006 at 04:00:46PM +0100, nicolas inglart wrote: > Hi all, > > I don't understand why the value of the counter DATA_EAR_CACHE4 and the > counter L1D_READ_MISSES_ALL are different. > This is a good question. The answer is fairly simple.
The DATA_EAR_CACHE_LAT4 event does not count ALL the L1D cache misses but only the ones that are tracked by the Data-EAR. The Data EAR does not track all L1D misses by construction. As you realize once a load is selected to be tracked by the Data EAR, no other load can be tracked until the Data EAR record is complete, i.e., until the miss latency is known which happens when the missing data is brought into the L1D cache. During that time, other loads in the "shadow" of the track load may miss and they will be counted by L1D_READ_MISSES_ALL but not by DATA_EAR_CACHE_*. So I would expect that the DATA_EAR_CACHE_LAT4 count will always be lower or equal to L1D_READ_MISSES_ALL. Hope this helps. -- -Stephane _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
