Hello Stephane,
> All your patches to support IBM Cell processor for libpfm have been
> pushed to the CVS repository. Please pull from it, and let me know if
> it works for you.
I am sorry for late reply. It works! Thank you.
Now I found the difference between the patch that I released the other day and
libpfm that had been released.
Moreover, I changed pme_code to conform to kernel-patch.
I release the patch that corrects these problems.
Thanks,
--Yoshio Funayama
Signed-off-by: Yoshio Funayama <[EMAIL PROTECTED]>
Signed-off-by: Takayuki Uchikawa <[EMAIL PROTECTED]>
Index: libpfm/include/perfmon/perfmon.h
===================================================================
--- libpfm_org/include/perfmon/perfmon.h
+++ libpfm/include/perfmon/perfmon.h
@@ -31,10 +31,6 @@ extern "C" {
#include <perfmon/perfmon_powerpc.h>
#endif
-#ifdef __cell__
-#include <perfmon/perfmon_powerpc.h>
-#endif
-
#ifdef __mips__
#include <perfmon/perfmon_mips64.h>
#endif
@@ -325,10 +321,6 @@ extern int pfm_unload_context(int fd);
#define __NR_pfm_create_context 310
#endif
-#ifdef __cell__
-#define __NR_pfm_create_context 309
-#endif
-
#ifdef __crayx2
#define __NR_pfm_create_context 294
#endif
Index: libpfm/include/perfmon/pfmlib_comp.h
===================================================================
--- libpfm_org/include/perfmon/pfmlib_comp.h
+++ libpfm/include/perfmon/pfmlib_comp.h
@@ -42,10 +42,6 @@
#include <perfmon/pfmlib_comp_powerpc.h>
#endif
-#ifdef __cell__
-#include <perfmon/pfmlib_comp_powerpc.h>
-#endif
-
#ifdef __crayx2
#include <perfmon/pfmlib_comp_crayx2.h>
#endif
Index: libpfm/include/perfmon/pfmlib_os.h
===================================================================
--- libpfm_org/include/perfmon/pfmlib_os.h
+++ libpfm/include/perfmon/pfmlib_os.h
@@ -42,10 +42,6 @@
#include <perfmon/pfmlib_os_powerpc.h>
#endif
-#ifdef __cell__
-#include <perfmon/pfmlib_os_powerpc.h>
-#endif
-
#ifdef __crayx2
#include <perfmon/pfmlib_os_crayx2.h>
#endif
Index: libpfm/lib/cell_events.h
===================================================================
--- libpfm_org/lib/cell_events.h
+++ libpfm/lib/cell_events.h
@@ -78,30 +78,30 @@ static pme_cell_entry_t cell_pe[] = {
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_OCCURRENCE,
},
- {.pme_name = "23_2",
+ {.pme_name = "22_2",
.pme_desc = " Data effective-address-to-real-address translation
(D-ERAT) miss. This event is not speculative. ",
- .pme_code = 0x8fe,
+ .pme_code = 0x89a,
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "23_3",
+ {.pme_name = "22_3",
.pme_desc = " Store request counted at the L2 interface. This counts
microcoded PowerPC Processor Element (PPE) sequences more than once (see Note 1
for exceptions). ",
- .pme_code = 0x8ff,
+ .pme_code = 0x89b,
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "23_4",
+ {.pme_name = "22_4",
.pme_desc = " Load valid at a particular pipe stage. This is
speculative because flushed operations are also counted. Counts microcoded PPE
sequences more than once. Misaligned flushes might be counted the first time as
well. Load operations include all loads that read data from the cache, dcbt and
dcbtst. This event does not include load Vector/single instruction multiple
data (SIMD) multimedia extension pattern instructions. ",
- .pme_code = 0x900,
+ .pme_code = 0x89c,
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
},
- {.pme_name = "23_5",
+ {.pme_name = "22_5",
.pme_desc = " L1 D-cache load miss. Pulsed when there is a miss
request that has a tag miss but not an effective-address-to-real-address
translation (ERAT) miss. This is speculative because flushed operations are
counted as well. ",
- .pme_code = 0x901,
+ .pme_code = 0x89d,
.pme_enable_word = WORD_0_AND_1,
.pme_freq = PFM_CELL_PME_FREQ_PPU_MFC,
.pme_type = COUNT_TYPE_CUMULATIVE_LEN,
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