Stephane Eranian wrote:
Will,
I have applied your patch.
I would suggest you pull the latest core_events.h from CVS and update the
Oprofile
event list. I have updated my list with the latest infos from Intel. There are
some changes concerning certain events which can only be measured on counter 0
or 1.
Grep for PMC0 and PMC1 in the file. Also note that there is a new event called
RS_UOPS_DISPATCHED:PORT* in the documentation. In my table it is called
RS_UOPS_DISPATCHED_CYCLES as it measures cycles to avoid confusion with
RS_UOPS_DISPATCHED (no unit mask) which is counting uops retired.
Last time I looked at Oprofile fore Core, it did not have the counter
constraints right.
Thanks for your contributions.
Hi Stephane,
I can probably roll that in with some changes for the core2 events names that I
would like tot get checked in for oprofile based on the following bug report:
https://bugzilla.redhat.com/show_bug.cgi?id=234732
The changes for core 2 are based off the Documentation Intel has at the
following link?
http://www.intel.com/products/processor/manuals/index.htm
-Will
On Thu, Sep 13, 2007 at 05:03:43PM -0400, William Cohen wrote:
William Cohen wrote:
Hi,
I was playing around with the events this afternoon to find out what
kind of TLB miss rates I was getting on my machine. I found a couple of
typos amd64_events.h in libpfm cvs. Attached is a patch that correct the
TLB event names and descriptions.
-Will
Let's try that again with the correct file. -Will
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