Hello Rob, On Fri, Oct 19, 2007 at 12:42:54AM -0400, Rob Fowler wrote: > We've got a tool stack consisting of HPCToolkit (SVN trunk) + PAPI (CVS > head) + Perfmon2 > up and running on a box with Barcelona processors. Everything's > working just fine, but the event definitions in libpfm/lib/amd64_events.h > don't cover the new Barcelona evens, e.g., the L3 cache events. > Yes, I know that.
> I checked the latest tarball on sourceforge, as well as the CVS tree, to > confirm that we're running with the latest at that site. > > Questions: Has anyone out there gone through the exercise of extending the > event table for Barcelona yet? > Not yet. I am working with AMD on this and they are supposed to provide the Barcelona event table. This task is best done by HW vendors themselves because they have the tables in electronic format already and also because it ensures everybody gets the official event names. > If not, what's the approved strategy for doing this? Since this is a > model-specific extension, my guess is to add the extended event set > in a separate .h file, i.e., follow the itanium/itanium2/montecito example. I think using a separate header file would be cleaner. Tthe detection routine would then initialize a pointer to either table. BTW, the kernel GIT tree (as of a couple of days ago) provides support for Barcelona IBS as well. Thanks to AMD. -- -Stephane _______________________________________________ perfmon mailing list [email protected] http://www.hpl.hp.com/hosted/linux/mail-archives/perfmon/
