PS3 PMU(Performance Monitor Unit) support.
This patch adds PS3 PMU functions.
They use PS3 lv1 call(hypervisor call)s to control the HW performance
monitor.
Signed-off-by: Takashi Yamamoto <TakashiA.Yamamoto at jp.sony.com>
---
arch/powerpc/platforms/ps3/Kconfig | 12
arch/powerpc/platforms/ps3/Makefile | 1
arch/powerpc/platforms/ps3/platform.h | 9
arch/powerpc/platforms/ps3/pmu.c | 1049
++++++++++++++++++++++++++++++++
arch/powerpc/platforms/ps3/repository.c | 47 +
include/asm-powerpc/ps3.h | 65 +
6 files changed, 1183 insertions(+)
Index: linux-2.6/arch/powerpc/platforms/ps3/Kconfig
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/ps3/Kconfig
+++ linux-2.6/arch/powerpc/platforms/ps3/Kconfig
@@ -138,4 +138,16 @@ config PS3_FLASH
be disabled on the kernel command line using "ps3flash=off", to
not allocate this fixed buffer.
+config PS3_PMU
+ bool "PS3 Performance Monitor Unit"
+ depends on PPC_PS3 && (PERFMON_CELL || OPROFILE_CELL)
+ default y
+ help
+ This support is required to access the Cell hardware performance
+ monitor on PS3.
+
+ To control the Cell hardware performance monitor,
+ It uses the performance monitor hypervisor calls instead of
+ the performane monitor register access.
+
endmenu
Index: linux-2.6/arch/powerpc/platforms/ps3/Makefile
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/ps3/Makefile
+++ linux-2.6/arch/powerpc/platforms/ps3/Makefile
@@ -5,3 +5,4 @@ obj-y += system-bus.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SPU_BASE) += spu.o
obj-y += device-init.o
+obj-$(CONFIG_PS3_PMU) += pmu.o
Index: linux-2.6/arch/powerpc/platforms/ps3/platform.h
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/ps3/platform.h
+++ linux-2.6/arch/powerpc/platforms/ps3/platform.h
@@ -203,12 +203,21 @@ int ps3_repository_read_be_node_id(unsig
int ps3_repository_read_tb_freq(u64 node_id, u64 *tb_freq);
int ps3_repository_read_be_tb_freq(unsigned int be_index, u64 *tb_freq);
+/* repository performance monitor info */
+
+int ps3_repository_read_lpm_priv(unsigned int be_index, u64 *lpar, u64
*priv);
+
/* repository 'Other OS' area */
int ps3_repository_read_boot_dat_addr(u64 *lpar_addr);
int ps3_repository_read_boot_dat_size(unsigned int *size);
int ps3_repository_read_boot_dat_info(u64 *lpar_addr, unsigned int *size);
+/* repository pu info */
+
+int ps3_repository_read_num_pu(unsigned int *num_pu);
+int ps3_repository_read_pu_id(unsigned int pu_index, u64 *pu_id);
+
/* repository spu info */
/**
Index: linux-2.6/arch/powerpc/platforms/ps3/pmu.c
===================================================================
--- /dev/null
+++ linux-2.6/arch/powerpc/platforms/ps3/pmu.c
@@ -0,0 +1,1050 @@
+/*
+ * PS3 Logical Performance Monitor Unit.
+ *
+ * Copyright (C) 2007 Sony Computer Entertainment Inc.
+ * Copyright 2007 Sony Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307 USA
+ */
+
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/irq_regs.h>
+#include <asm/machdep.h>
+#include <asm/pmc.h>
+#include <asm/reg.h>
+#include <asm/spu.h>
+#include <asm/lv1call.h>
+#include <asm/ps3.h>
+#include <asm/cell-pmu.h>
+#include "platform.h"
+
+#define PMU_ERR(f, x...) pr_info("pmu: " f "\n", ## x)
+#define PMU_INFO(f, x...) pr_info("pmu: " f "\n", ## x)
+#define PMU_DBG(f, x...) pr_debug("pmu: " f "\n", ## x)
+
+/*
+ * USE_START_STOP_BOOKMARK enables the PPU bookmark trace.
+ * And it enables PPU bookmark triggers ONLY if the other triggers are not
set.
+ * The start/stop bookmarks are inserted at ps3_enable_pm() and
ps3_disable_pm()
+ * to start/stop PMU.
+ *
+ * This macro is used to get good quality of the performance counter.
+ */
+#define USE_START_STOP_BOOKMARK
+
+/* BOOKMARK tag macros */
+#define PS3_PM_BOOKMARK_START 0x8000000000000000ULL
+#define PS3_PM_BOOKMARK_STOP 0x4000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_KERNEL 0x1000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_USER 0x3000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_MASK_HI 0xF000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_MASK_LO 0x0F00000000000000ULL
+
+/* CBE PM CONTROL register macros */
+#define PS3_PM_CONTROL_PPU_TH0_BOOKMARK 0x00001000
+#define PS3_PM_CONTROL_PPU_TH1_BOOKMARK 0x00000800
+#define PS3_PM_CONTROL_PPU_COUNT_MODE_MASK 0x000C0000
+#define PS3_PM_CONTROL_PPU_COUNT_MODE_PROBLEM 0x00080000
+#define PS3_WRITE_PM_MASK 0xFFFFFFFFFFFFFFFFULL
+
+/* CBE PM START STOP register macros */
+#define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START 0x02000000
+#define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START 0x01000000
+#define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP 0x00020000
+#define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP 0x00010000
+#define PS3_PM_START_STOP_START_MASK 0xFF000000
+#define PS3_PM_START_STOP_STOP_MASK 0x00FF0000
+
+/* CBE PM COUNTER register macres */
+#define PS3_PM_COUNTER_MASK_HI 0xFFFFFFFF00000000ULL
+#define PS3_PM_COUNTER_MASK_LO 0x00000000FFFFFFFFULL
+
+/* BASE SIGNAL GROUP NUMBER macros */
+#define PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER 0
+#define PM_ISLAND2_SIGNAL_GROUP_NUMBER1 6
+#define PM_ISLAND2_SIGNAL_GROUP_NUMBER2 7
+#define PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER 7
+#define PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER 15
+#define PM_SPU_TRIGGER_SIGNAL_GROUP_NUMBER 17
+#define PM_SPU_EVENT_SIGNAL_GROUP_NUMBER 18
+#define PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER 18
+#define PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER 24
+#define PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER 49
+#define PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER 52
+#define PM_SIG_GROUP_SPU 41
+#define PM_SIG_GROUP_SPU_TRIGGER 42
+#define PM_SIG_GROUP_SPU_EVENT 43
+#define PM_SIG_GROUP_MFC_MAX 60
+
+/* shadow register macros */
+#define PS3_SHADOW_REG_INIT_VALUE 0xFFFFFFFF00000000ULL
+
+/* bookmark spr address */
+#define BOOKMARK_SPR_ADDR 1020
+
+/* PS3 logical performance monitor context */
+static struct ps3_lpm_context ps3_lpm;
+
+/* lock for ps3_lpm context */
+static __cacheline_aligned_in_smp DEFINE_SPINLOCK(ps3_lpm_lock);
+
+inline struct ps3_lpm_context *ps3_get_lpm_context(void)
+{
+ return &ps3_lpm;
+}
+EXPORT_SYMBOL_GPL(ps3_get_lpm_context);
+
+inline void ps3_set_bookmark(u64 bookmark)
+{
+ /*
+ * To avoid bookmark lost, the following nops are added.
+ */
+ asm volatile("nop;nop;nop;nop;nop;nop;nop;nop;nop;");
+ mtspr(BOOKMARK_SPR_ADDR, bookmark);
+ asm volatile("nop;nop;nop;nop;nop;nop;nop;nop;nop;");
+}
+EXPORT_SYMBOL_GPL(ps3_set_bookmark);
+
+inline void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id)
+{
+ u64 bookmark;
+
+ bookmark = (get_tb() & 0x00000000FFFFFFFFULL) |
+ PS3_PM_BOOKMARK_TAG_KERNEL;
+ bookmark = ((tag << 56) & PS3_PM_BOOKMARK_TAG_MASK_LO) |
+ (incident << 48) | (th_id << 32) | bookmark;
+ ps3_set_bookmark(bookmark);
+}
+EXPORT_SYMBOL_GPL(ps3_set_pm_bookmark);
+
+/*
+ * Read physical counter registers.
+ * Each physical counter can act as one 32-bit counter or two 16-bit
counters.
+ */
+u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr)
+{
+ u32 val = 0;
+ u64 counter0415;
+ u64 counter2637;
+ int ret;
+
+ if (phys_ctr < NR_PHYS_CTRS) {
+ ret = lv1_set_lpm_counter(ps3_lpm.id, 0, 0, 0, 0,
+ &counter0415, &counter2637);
+ switch (phys_ctr) {
+ case 0:
+ val = (u32)(counter0415 >> 32);
+ break;
+ case 1:
+ val = (u32)(counter0415 & PS3_PM_COUNTER_MASK_LO);
+ break;
+ case 2:
+ val = (u32)(counter2637 >> 32);
+ break;
+ case 3:
+ val = (u32)(counter2637 & PS3_PM_COUNTER_MASK_LO);
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ if (ret)
+ PMU_ERR("%s cnum:%d error:%d",
+ __FUNCTION__, phys_ctr, ret);
+ }
+ return val;
+}
+EXPORT_SYMBOL_GPL(ps3_read_phys_ctr);
+
+/*
+ * Write physical counter registers.
+ * Each physical counter can act as one 32-bit counter or two 16-bit
counters.
+ */
+void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
+{
+ u64 counter0415;
+ u64 counter0415_mask;
+ u64 counter2637;
+ u64 counter2637_mask;
+ int ret;
+ u64 tmp;
+
+ ret = 0;
+ tmp = val;
+ if (phys_ctr < NR_PHYS_CTRS) {
+ switch (phys_ctr) {
+ case 0:
+ counter0415 = tmp << 32;
+ counter0415_mask = PS3_PM_COUNTER_MASK_HI;
+ counter2637 = 0x0;
+ counter2637_mask = 0x0;
+ break;
+ case 1:
+ counter0415 = tmp;
+ counter0415_mask = PS3_PM_COUNTER_MASK_LO;
+ counter2637 = 0x0;
+ counter2637_mask = 0x0;
+ break;
+ case 2:
+ counter0415 = 0x0;
+ counter0415_mask = 0x0;
+ counter2637 = tmp << 32;
+ counter2637_mask = PS3_PM_COUNTER_MASK_HI;
+ break;
+ case 3:
+ counter0415 = 0x0;
+ counter0415_mask = 0x0;
+ counter2637 = tmp;
+ counter2637_mask = PS3_PM_COUNTER_MASK_LO;
+ break;
+ default:
+ return ;
+ }
+
+ ret = lv1_set_lpm_counter(ps3_lpm.id,
+ counter0415, counter0415_mask,
+ counter2637, counter2637_mask,
+ &counter0415, &counter2637);
+ if (ret)
+ PMU_ERR("%s cnum:%d value:0x%x error:%d",
+ __FUNCTION__, phys_ctr, val, ret);
+ }
+}
+EXPORT_SYMBOL_GPL(ps3_write_phys_ctr);
+
+/*
+ * read 16-bits or 32-bits depending on the
+ * current size of the counter. Counters 4 - 7 are always 16-bit.
+ */
+u32 ps3_read_ctr(u32 cpu, u32 ctr)
+{
+ u32 val;
+ u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
+
+ val = ps3_read_phys_ctr(cpu, phys_ctr);
+
+ if (ps3_get_ctr_size(cpu, phys_ctr) == 16)
+ val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
+
+ return val;
+}
+EXPORT_SYMBOL_GPL(ps3_read_ctr);
+
+/*
+ * write 16-bits or 32-bits depending on the
+ * current size of the counter. Counters 4 - 7 are always 16-bit.
+ */
+void ps3_write_ctr(u32 cpu, u32 ctr, u32 val)
+{
+ u32 phys_ctr;
+ u32 phys_val;
+
+ phys_ctr = ctr & (NR_PHYS_CTRS - 1);
+
+ if (ps3_get_ctr_size(cpu, phys_ctr) == 16) {
+ phys_val = ps3_read_phys_ctr(cpu, phys_ctr);
+
+ if (ctr < NR_PHYS_CTRS)
+ val = (val << 16) | (phys_val & 0xffff);
+ else
+ val = (val & 0xffff) | (phys_val & 0xffff0000);
+ }
+
+ ps3_write_phys_ctr(cpu, phys_ctr, val);
+}
+EXPORT_SYMBOL_GPL(ps3_write_ctr);
+
+/*
+ * Read Counter-control registers.
+ * Each "logical" counter has a corresponding control register.
+ */
+u32 ps3_read_pm07_control(u32 cpu, u32 ctr)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_read_pm07_control);
+
+/*
+ * Write Counter-control registers.
+ * Each "logical" counter has a corresponding control register.
+ */
+void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val)
+{
+ u64 mask;
+ u64 old_value;
+ int ret;
+
+ if (ctr < NR_CTRS) {
+ mask = 0xFFFFFFFFFFFFFFFFULL;
+ ret = lv1_set_lpm_counter_control(ps3_lpm.id, ctr,
+ val, mask, &old_value);
+ if (ret)
+ PMU_ERR("%s cnum:%d value:0x%x error:%d",
+ __FUNCTION__, ctr, val, ret);
+ }
+}
+EXPORT_SYMBOL_GPL(ps3_write_pm07_control);
+
+/*
+ * Read Other PMU control registers.
+ */
+u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg)
+{
+ u32 val = 0;
+
+ switch (reg) {
+ case pm_control:
+ val = ps3_lpm.shadow_pm_control;
+ break;
+ case trace_address:
+ val = CBE_PM_TRACE_BUF_EMPTY;
+ break;
+ case pm_start_stop:
+ val = ps3_lpm.shadow_pm_start_stop;
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ return val;
+}
+EXPORT_SYMBOL_GPL(ps3_read_pm);
+
+/*
+ * Write Other PMU control registers.
+ */
+void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
+{
+ int ret;
+ u64 dummy;
+
+ ret = 0;
+ switch (reg) {
+ case group_control:
+ if (val != ps3_lpm.shadow_group_control)
+ ret = lv1_set_lpm_group_control(ps3_lpm.id, val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ ps3_lpm.shadow_group_control = val;
+ break;
+
+ case debug_bus_control:
+ if (val != ps3_lpm.shadow_debug_bus_control)
+ ret = lv1_set_lpm_debug_bus_control(ps3_lpm.id, val,
+
PS3_WRITE_PM_MASK,
+ &dummy);
+ ps3_lpm.shadow_debug_bus_control = val;
+ break;
+
+ case pm_control:
+ /*
+ * count mode is always problem-mode.
+ * because lv-1 lpm allows only problem-mode.
+ */
+ val = (val & ~PS3_PM_CONTROL_PPU_COUNT_MODE_MASK) |
+ PS3_PM_CONTROL_PPU_COUNT_MODE_PROBLEM;
+#ifdef USE_START_STOP_BOOKMARK
+ val = val | PS3_PM_CONTROL_PPU_TH0_BOOKMARK |
+ PS3_PM_CONTROL_PPU_TH1_BOOKMARK ;
+#endif
+ if (val != ps3_lpm.shadow_pm_control)
+ ret = lv1_set_lpm_general_control(ps3_lpm.id, val,
+ PS3_WRITE_PM_MASK,
+ 0, 0,
+ &dummy, &dummy);
+ ps3_lpm.shadow_pm_control = val;
+ break;
+
+ case pm_interval:
+ if (val != ps3_lpm.shadow_pm_interval)
+ ret = lv1_set_lpm_interval(ps3_lpm.id, val,
+ PS3_WRITE_PM_MASK,
&dummy);
+ ps3_lpm.shadow_pm_interval = val;
+ break;
+
+ case pm_start_stop:
+ if (val != ps3_lpm.shadow_pm_start_stop)
+ ret = lv1_set_lpm_trigger_control(ps3_lpm.id, val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ ps3_lpm.shadow_pm_start_stop = val;
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ if (ret)
+ PMU_ERR("%s reg:%d value:0x%x error:%d",
+ __FUNCTION__, reg, val, ret);
+}
+EXPORT_SYMBOL_GPL(ps3_write_pm);
+
+/*
+ * Get the size of a physical counter to either 16 or 32 bits.
+ */
+u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr)
+{
+ u32 pm_ctrl, size = 0;
+
+ if (phys_ctr < NR_PHYS_CTRS) {
+ pm_ctrl = ps3_read_pm(cpu, pm_control);
+ size = (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
+ }
+
+ return size;
+}
+EXPORT_SYMBOL_GPL(ps3_get_ctr_size);
+
+/*
+ * Set the size of a physical counter to either 16 or 32 bits.
+ */
+void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
+{
+ u32 pm_ctrl;
+
+ if (phys_ctr < NR_PHYS_CTRS) {
+ pm_ctrl = ps3_read_pm(cpu, pm_control);
+ switch (ctr_size) {
+ case 16:
+ pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
+ break;
+
+ case 32:
+ pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
+ break;
+ }
+ ps3_write_pm(cpu, pm_control, pm_ctrl);
+ }
+}
+EXPORT_SYMBOL_GPL(ps3_set_ctr_size);
+
+static inline u64 pm_translate_signal_group_number_on_island2(
+ u64 subgroup)
+{
+
+ if (subgroup == 2)
+ subgroup = 3;
+
+ if (subgroup <= 6)
+ return PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+ else if (subgroup == 7)
+ return PM_ISLAND2_SIGNAL_GROUP_NUMBER1;
+ else
+ return PM_ISLAND2_SIGNAL_GROUP_NUMBER2;
+}
+
+static inline u64 pm_translate_signal_group_number_on_island3(
+ u64 subgroup)
+{
+
+ switch (subgroup) {
+ case 2:
+ case 3:
+ case 4:
+ subgroup += 2;
+ break;
+ case 5:
+ subgroup = 8;
+ break;
+ default:
+ break;
+ }
+ return PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static inline u64 pm_translate_signal_group_number_on_island4(
+ u64 subgroup) {
+ return PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static inline u64 pm_translate_signal_group_number_on_island5(
+ u64 subgroup)
+{
+
+ switch (subgroup) {
+ case 3:
+ subgroup = 4;
+ break;
+ case 4:
+ subgroup = 6;
+ break;
+ default:
+ break;
+ }
+ return PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static inline u64 pm_translate_signal_group_number_on_island6(
+ u64 subgroup, u64 subsubgroup)
+{
+ switch (subgroup) {
+ case 3:
+ case 4:
+ case 5:
+ subgroup += 1;
+ break;
+ default:
+ break;
+ }
+
+ switch (subsubgroup) {
+ case 4:
+ case 5:
+ case 6:
+ subsubgroup += 2;
+ break;
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ subsubgroup += 4;
+ break;
+ case 11:
+ case 12:
+ case 13:
+ subsubgroup += 5;
+ break;
+ default:
+ break;
+ }
+
+ if (subgroup <= 5)
+ return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup);
+ else
+ return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup
+ + subsubgroup - 1);
+}
+
+static inline u64 pm_translate_signal_group_number_on_island7(
+ u64 subgroup)
+{
+ return PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static inline u64 pm_translate_signal_group_number_on_island8(
+ u64 subgroup)
+{
+ return PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_signal_group_to_ps3_lv1_signal_group(u64 group)
+{
+ u64 island;
+ u64 subgroup;
+ u64 subsubgroup;
+ u64 lv1_signal_group;
+
+ subgroup = 0;
+ subsubgroup = 0;
+ if (group < 1000) {
+ if (group < 100) {
+ if (20 <= group && group < 30) {
+ island = 2;
+ subgroup = group - 20;
+ } else if (30 <= group && group < 40) {
+ island = 3;
+ subgroup = group - 30;
+ } else if (40 <= group && group < 50) {
+ island = 4;
+ subgroup = group - 40;
+ } else if (50 <= group && group < 60) {
+ island = 5;
+ subgroup = group - 50;
+ } else if (60 <= group && group < 70) {
+ island = 6;
+ subgroup = group - 60;
+ } else if (70 <= group && group < 80) {
+ island = 7;
+ subgroup = group - 70;
+ } else if (80 <= group && group < 90) {
+ island = 8;
+ subgroup = group - 80;
+ } else {
+ island = 0;
+ }
+ } else if (200 <= group && group < 300) {
+ island = 2;
+ subgroup = group - 200;
+ } else if (600 <= group && group < 700) {
+ island = 6;
+ subgroup = 5;
+ subsubgroup = group - 650;
+ } else {
+ island = 0;
+ }
+ } else if (6000 <= group && group < 7000) {
+ island = 6;
+ subgroup = 5;
+ subsubgroup = group - 6500;
+ } else {
+ island = 0;
+ }
+
+ switch (island) {
+ case 2:
+ lv1_signal_group =
+
pm_translate_signal_group_number_on_island2(subgroup);
+ break;
+ case 3:
+ lv1_signal_group =
+
pm_translate_signal_group_number_on_island3(subgroup);
+ break;
+ case 4:
+ lv1_signal_group =
+
pm_translate_signal_group_number_on_island4(subgroup);
+ break;
+ case 5:
+ lv1_signal_group =
+
pm_translate_signal_group_number_on_island5(subgroup);
+ break;
+ case 6:
+ lv1_signal_group =
+ pm_translate_signal_group_number_on_island6(
+ subgroup, subsubgroup);
+ break;
+ case 7:
+ lv1_signal_group =
+
pm_translate_signal_group_number_on_island7(subgroup);
+ break;
+ case 8:
+ lv1_signal_group =
+
pm_translate_signal_group_number_on_island8(subgroup);
+ break;
+ default:
+ lv1_signal_group = 0;
+ break;
+ }
+ return lv1_signal_group;
+}
+
+static u64 pm_bus_word_to_ps3_lv1_bus_word(u8 word)
+{
+
+ switch (word) {
+ case 1:
+ return 0xF000;
+ case 2:
+ return 0x0F00;
+ case 4:
+ return 0x00F0;
+ case 8:
+ default:
+ return 0x000F;
+ }
+}
+
+static int __ps3_set_signal(u64 lv1_signal_group, u64 bus_select,
+ u64 signal_select, u64 attr1, u64 attr2, u64
attr3)
+{
+ int ret;
+
+ ret = lv1_set_lpm_signal(ps3_lpm.id, lv1_signal_group, bus_select,
+ signal_select, attr1, attr2, attr3);
+ if (ret)
+ PMU_ERR("%s error:%d 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx",
+ __FUNCTION__, ret,
+ lv1_signal_group, bus_select, signal_select, attr1,
+ attr2, attr3);
+
+ return ret;
+}
+
+int ps3_set_signal(u64 signal_group, u8 signal_bit, u16 sub_unit,
+ u8 bus_word)
+{
+ int ret;
+ u64 lv1_signal_group;
+ u64 bus_select;
+ u64 signal_select;
+ u64 attr1, attr2, attr3;
+
+ if (signal_group == 0)
+ return __ps3_set_signal(0, 0, 0, 0, 0, 0);
+
+ lv1_signal_group =
+ pm_signal_group_to_ps3_lv1_signal_group(signal_group);
+ bus_select = pm_bus_word_to_ps3_lv1_bus_word(bus_word);
+
+ switch (signal_group) {
+ case PM_SIG_GROUP_SPU_TRIGGER:
+ signal_select = 1;
+ signal_select = signal_select << (63 - signal_bit);
+ break;
+ case PM_SIG_GROUP_SPU_EVENT:
+ signal_select = 1;
+ signal_select = (signal_select << (63 - signal_bit)) | 0x3;
+ break;
+ default:
+ signal_select = 0;
+ break;
+ }
+
+ /*
+ * 0: physical object.
+ * 1: logical object.
+ * This parameter is only used for the PPE and SPE signals.
+ */
+ attr1 = 1;
+
+ /*
+ * This parameter is used to specify the target physical/logical
+ * PPE/SPE object.
+ */
+ if (PM_SIG_GROUP_SPU <= signal_group &&
+ signal_group < PM_SIG_GROUP_MFC_MAX) {
+ attr2 = sub_unit;
+ } else {
+ attr2 = ps3_lpm.pu_id;;
+ }
+
+ /*
+ * This parameter is only used for setting the SPE signal.
+ */
+ attr3 = 0;
+
+ ret = __ps3_set_signal(lv1_signal_group,
+ bus_select,
+ signal_select,
+ attr1,
+ attr2,
+ attr3);
+ if (ret)
+ PMU_ERR("%s error:%d", __FUNCTION__, ret);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ps3_set_signal);
+
+inline u32 ps3_get_hw_thread_id(int cpu)
+{
+ return cpu;
+}
+EXPORT_SYMBOL_GPL(ps3_get_hw_thread_id);
+
+
+/*
+ * Enable the entire performance monitoring unit.
+ * When we enable the PMU, all pending writes to counters get committed.
+ */
+void ps3_enable_pm(u32 cpu)
+{
+ int ret;
+ u64 tmp;
+ u32 tb;
+
+#ifdef USE_START_STOP_BOOKMARK
+ int insert_bookmark = 0;
+ if (!(ps3_lpm.shadow_pm_start_stop &
+ (PS3_PM_START_STOP_START_MASK | PS3_PM_START_STOP_STOP_MASK)))
{
+ ret = lv1_set_lpm_trigger_control(
+ ps3_lpm.id,
+ (PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START |
+ PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START |
+ PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP |
+ PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP),
+ 0xFFFFFFFFFFFFFFFFULL,
+ &tmp);
+ insert_bookmark = 1;
+ }
+#endif
+ ret = lv1_start_lpm(ps3_lpm.id);
+ if (ret)
+ PMU_ERR("Lv-1 lpm: start lpm error");
+
+#ifdef USE_START_STOP_BOOKMARK
+ if (insert_bookmark) {
+ tb = get_tb();
+ ps3_set_bookmark(PS3_PM_BOOKMARK_START | tb);
+ }
+#endif
+}
+EXPORT_SYMBOL_GPL(ps3_enable_pm);
+
+/*
+ * Disable the entire performance monitoring unit.
+ */
+void ps3_disable_pm(u32 cpu)
+{
+ int ret;
+ u64 param = 0;
+ u32 tb;
+
+ tb = get_tb();
+ ps3_set_bookmark(PS3_PM_BOOKMARK_STOP | tb);
+
+ ret = lv1_stop_lpm(ps3_lpm.id, ¶m);
+ if (!ret) {
+ ps3_lpm.sizeof_traced_data = param;
+ ps3_lpm.sizeof_total_copied_data = 0;
+ }
+}
+EXPORT_SYMBOL_GPL(ps3_disable_pm);
+
+/*
+ * Copy the trace buffer.
+ */
+static u64 _ps3_copy_trace_buffer(u64 offset, u64 size, u64 *to, int
to_user)
+{
+ int ret;
+ u64 sizeof_copied_data;
+
+ if (offset >= ps3_lpm.sizeof_traced_data)
+ return 0;
+
+ ret = lv1_copy_lpm_trace_buffer(ps3_lpm.id, offset, size,
+ &sizeof_copied_data);
+ if (ret) {
+ PMU_ERR("lv1_copy_lpm_trace_buffer error:%d "
+ "offset:0x%lx size:0x%lx", ret, offset, size);
+ return 0;
+ }
+
+ if (to_user) {
+ if (copy_to_user((void __user *)to, ps3_lpm.tb_cache,
+ sizeof_copied_data)) {
+ PMU_ERR("copy_to_user() error. "
+ "offset:0x%lx size:0x%lx dest:0x%p
src:0x%p",
+ offset, sizeof_copied_data, to,
+ ps3_lpm.tb_cache);
+ return 0;
+ }
+ } else
+ memcpy(to, ps3_lpm.tb_cache, sizeof_copied_data);
+
+ return sizeof_copied_data;
+}
+u64 ps3_copy_trace_buffer(u64 offset, u64 size, void *to, int to_user)
+{
+ u64 sz;
+ u64 cp_size;
+ u64 total_cp_size;
+
+ if (!ps3_lpm.tb_cache)
+ return 0;
+
+ cp_size = size;
+ if (cp_size > ps3_lpm.sizeof_tb_cache)
+ cp_size = ps3_lpm.sizeof_tb_cache;
+
+ total_cp_size = 0;
+ while (total_cp_size < size) {
+ sz = _ps3_copy_trace_buffer(offset, cp_size, to, to_user);
+ if (!sz)
+ break;
+
+ total_cp_size += sz;
+ offset += sz;
+ to = ((u8 *)to + sz);
+ }
+ return total_cp_size;
+}
+
+/*
+ * Clearing interrupts for the entire performance monitoring unit.
+ */
+u32 ps3_get_and_clear_pm_interrupts(u32 cpu)
+{
+ /* Reading pm_status clears the interrupt bits. */
+ return ps3_read_pm(cpu, pm_status);
+}
+EXPORT_SYMBOL_GPL(ps3_get_and_clear_pm_interrupts);
+
+/*
+ * Enabling interrupts for the entire performance monitoring unit.
+ */
+void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
+{
+ /* Enable the interrupt bits in the pm_status register. */
+ if (mask)
+ ps3_write_pm(cpu, pm_status, mask);
+}
+EXPORT_SYMBOL_GPL(ps3_enable_pm_interrupts);
+
+/*
+ * Disabling interrupts for the entire performance monitoring unit.
+ */
+void ps3_disable_pm_interrupts(u32 cpu)
+{
+ ps3_get_and_clear_pm_interrupts(cpu);
+ ps3_write_pm(cpu, pm_status, 0);
+}
+EXPORT_SYMBOL_GPL(ps3_disable_pm_interrupts);
+
+int ps3_create_lpm(int is_default_tb_cache,
+ void *tb_cache, u64 tb_cache_size, u64 tb_type)
+{
+ int ret;
+ u64 cbe_node_id;
+ u64 tb_size;
+ u64 ctrl_opt;
+ u64 tb_cache_lpar_addr;
+ u64 lpm_id;
+ u64 outlet_id;
+ u64 used_tb_size;
+
+ spin_lock(&ps3_lpm_lock);
+
+ if (ps3_lpm.constructed) {
+ PMU_ERR("construct Lv-1 lpm error. context state error.");
+ ret = -EBUSY;
+ goto unlock;
+ }
+
+ if (is_default_tb_cache) {
+ if (!ps3_lpm.default_tb_cache) {
+ ret = -ENOMEM;
+ goto unlock;
+ }
+
+ PMU_DBG("Use default TB cache");
+ tb_cache = ps3_lpm.default_tb_cache;
+ tb_cache_size = PS3_SIZE_OF_PM_DEFAULT_TRACE_BUFFER_CACHE;
+ }
+
+ cbe_node_id = 0;
+ if (tb_cache) {
+ if (tb_type == 0) {
+ /* no trace buffer */
+ tb_type = 0;
+ tb_size = 0;
+ ctrl_opt = 0;
+ tb_cache_lpar_addr = 0;
+ } else if (tb_type == 1) {
+ /* internal trace buffer */
+ tb_size = PS3_SIZE_OF_PM_INTERNAL_TRACE_BUFFER;
+ ctrl_opt = 0;
+ } else {
+ PMU_ERR("Unkown TB type:0x%lx", tb_type);
+ ret = -EINVAL;
+ goto unlock;
+ }
+ tb_cache_lpar_addr =
(u64)ps3_mm_phys_to_lpar(__pa(tb_cache));
+ } else {
+ /* no trace buffer */
+ tb_type = 0;
+ tb_size = 0;
+ ctrl_opt = 0;
+ tb_cache_lpar_addr = 0;
+ }
+
+ ret = lv1_construct_lpm(cbe_node_id, tb_type, tb_size, ctrl_opt,
+ tb_cache_lpar_addr, tb_cache_size,
+ &lpm_id, &outlet_id, &used_tb_size);
+ if (!ret) {
+ ps3_lpm.constructed = 1;
+ ps3_lpm.tb_cache = tb_cache;
+ ps3_lpm.sizeof_tb_cache = tb_cache_size;
+ ps3_lpm.id = lpm_id;
+ ps3_lpm.irq_outlet_id = outlet_id;
+ ps3_lpm.sizeof_tb = used_tb_size;
+ ps3_lpm.shadow_pm_control = PS3_SHADOW_REG_INIT_VALUE;
+ ps3_lpm.shadow_pm_start_stop = PS3_SHADOW_REG_INIT_VALUE;
+ ps3_lpm.shadow_pm_interval = PS3_SHADOW_REG_INIT_VALUE;
+ ps3_lpm.shadow_group_control = PS3_SHADOW_REG_INIT_VALUE;
+ ps3_lpm.shadow_debug_bus_control =
PS3_SHADOW_REG_INIT_VALUE;
+ PMU_DBG("Lv-1 lpm: id:0x%lx outlet:0x%lx sizeof_tb:0x%lx",
+ ps3_lpm.id, ps3_lpm.irq_outlet_id,
+ ps3_lpm.sizeof_tb);
+ ret = 0;
+ goto unlock;
+ } else {
+ PMU_ERR("construct Lv-1 lpm error:%d", ret);
+ ret = -EINVAL;
+ goto unlock;
+ }
+
+unlock:
+ spin_unlock(&ps3_lpm_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ps3_create_lpm);
+
+int ps3_delete_lpm(void)
+{
+ int ret;
+
+ spin_lock(&ps3_lpm_lock);
+
+ if (!ps3_lpm.constructed) {
+ PMU_ERR("destruct Lv-1 lpm error. context state error.");
+ ret = -ENOENT;
+ goto unlock;
+ }
+
+ ret = lv1_destruct_lpm(ps3_lpm.id);
+ if (!ret) {
+ ps3_lpm.constructed = 0;
+ PMU_DBG("destruct Lv-1 lpm. lpm_id:0x%lx", ps3_lpm.id);
+ ret = 0;
+ goto unlock;
+ } else {
+ PMU_ERR("destruct Lv-1 lpm. error:%d lpm_id:0x%lx",
+ ret, ps3_lpm.id);
+ ret = -EINVAL;
+ goto unlock;
+ }
+unlock:
+ spin_unlock(&ps3_lpm_lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ps3_delete_lpm);
+
+static int __init ps3_init(void)
+{
+ int ret;
+ unsigned int pun;
+ unsigned int i;
+ u64 pu_id;
+
+ ps3_lpm.constructed = 0;
+ ps3_lpm.default_tb_cache = NULL;
+
+ ret = ps3_repository_read_num_pu(&pun);
+ if (ret) {
+ PMU_ERR("Can't read bi.pun node");
+ return ret;
+ } else {
+ PMU_INFO("bi.pun : 0x%x", pun);
+ for (i = 0; i < pun; i++) {
+ ret = ps3_repository_read_pu_id(i, &pu_id);
+ if (ret) {
+ PMU_ERR("Can't read bi.pu%d node", i);
+ return -1;
+ }
+ PMU_INFO("ppe id : 0x%lx", pu_id);
+ ps3_lpm.pu_id = pu_id;
+ }
+ }
+
+ ret = ps3_repository_read_lpm_priv(0, &ps3_lpm.lpar_id,
&ps3_lpm.priv);
+ if (ret) {
+ PMU_ERR("Can't read be.0.lpm.priv node");
+ return -1;
+ } else {
+ PMU_INFO("be.0.lpm.priv : 0x%lx 0x%lx", ps3_lpm.lpar_id,
+ ps3_lpm.priv);
+ }
+
+ ps3_lpm.default_tb_cache =
+ kzalloc(PS3_SIZE_OF_PM_DEFAULT_TRACE_BUFFER_CACHE,
GFP_KERNEL);
+ if (!ps3_lpm.default_tb_cache)
+ PMU_ERR("Can't allocate default TB cache");
+
+ return 0;
+}
+arch_initcall(ps3_init);
Index: linux-2.6/arch/powerpc/platforms/ps3/repository.c
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/ps3/repository.c
+++ linux-2.6/arch/powerpc/platforms/ps3/repository.c
@@ -902,6 +902,53 @@ int ps3_repository_read_be_tb_freq(unsig
: ps3_repository_read_tb_freq(node_id, tb_freq);
}
+int ps3_repository_read_lpm_priv(unsigned int be_index, u64 *lpar, u64
*priv)
+{
+ int result;
+ u64 node_id;
+
+ *lpar = 0;
+ *priv = 0;
+ result = ps3_repository_read_be_node_id(be_index, &node_id);
+ return result ? result
+ : read_node(PS3_LPAR_ID_PME,
+ make_first_field("be", 0),
+ node_id,
+ make_field("lpm", 0),
+ make_field("priv", 0),
+ lpar, priv);
+}
+
+int ps3_repository_read_num_pu(unsigned int *num_pu)
+{
+ int result;
+ u64 v1;
+
+ v1 = 0;
+ result = read_node(PS3_LPAR_ID_CURRENT,
+ make_first_field("bi", 0),
+ make_field("pun", 0),
+ 0, 0,
+ &v1, NULL);
+ *num_pu = v1;
+ return result;
+}
+
+int ps3_repository_read_pu_id(unsigned int pu_index, u64 *pu_id)
+{
+ int result;
+ u64 v1;
+
+ v1 = 0;
+ result = read_node(PS3_LPAR_ID_CURRENT,
+ make_first_field("bi", 0),
+ make_field("pu", pu_index),
+ 0, 0,
+ &v1, NULL);
+ *pu_id = v1;
+ return result;
+}
+
#if defined(DEBUG)
int ps3_repository_dump_resource_info(const struct ps3_repository_device
*repo)
Index: linux-2.6/include/asm-powerpc/ps3.h
===================================================================
--- linux-2.6.orig/include/asm-powerpc/ps3.h
+++ linux-2.6/include/asm-powerpc/ps3.h
@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/device.h>
+#include "cell-pmu.h"
union ps3_firmware_version {
u64 raw;
@@ -438,5 +439,69 @@ struct ps3_prealloc {
extern struct ps3_prealloc ps3fb_videomemory;
extern struct ps3_prealloc ps3flash_bounce_buffer;
+#define PS3_SIZE_OF_PM_INTERNAL_TRACE_BUFFER 0x4000
+#define PS3_SIZE_OF_PM_DEFAULT_TRACE_BUFFER_CACHE 0x4000
+
+/*
+ * ps3_lpm_context : encapsulates all the state of the PS3 logical
+ * performance monitor.
+ */
+struct ps3_lpm_context {
+ int constructed;
+ u64 id; /* lv1 lpm id */
+ u64 irq_outlet_id; /* lv1 irq outlet id */
+ void *default_tb_cache;
+ u64 sizeof_tb; /* lv1's trace buffer size */
+ void *tb_cache; /* trace buffer cache */
+ u64 sizeof_tb_cache;
+ u64 sizeof_traced_data; /* traced data size */
+ u64 sizeof_total_copied_data;
+ u64 pu_id;
+ u64 shadow_pm_control;
+ u64 shadow_pm_start_stop;
+ u64 shadow_pm_interval;
+ u64 shadow_group_control;
+ u64 shadow_debug_bus_control;
+ u64 lpar_id;
+ u64 priv;
+};
+
+extern struct ps3_lpm_context *ps3_get_lpm_context(void);
+extern int ps3_create_lpm(int is_default_tb_cache,
+ void *tb_cache, u64 tb_cache_size, u64 tb_type);
+extern int ps3_delete_lpm(void);
+extern void ps3_set_bookmark(u64 bookmark);
+extern void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
+extern u64 ps3_copy_trace_buffer(u64 offset, u64 size, void *to, int
to_user);
+extern int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16
sub_unit,
+ u8 bus_word);
+
+/*
+ * The following functions are basically same as cbe functions(cell-pmu.h)
+ */
+extern u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
+extern void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
+extern u32 ps3_read_ctr(u32 cpu, u32 ctr);
+extern void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
+
+extern u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
+extern void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
+extern u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
+extern void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
+
+extern u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
+extern void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
+
+extern void ps3_enable_pm(u32 cpu);
+extern void ps3_disable_pm(u32 cpu);
+
+extern void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
+extern void ps3_disable_pm_interrupts(u32 cpu);
+extern u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
+extern void ps3_sync_irq(int node);
+
+extern u32 ps3_get_hw_thread_id(int cpu);
+
+extern u64 ps3_get_spe_id(void *arg);
#endif
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