On Tue, Nov 29, 2011 at 08:52, Dmitry Karpeev <karpeev at mcs.anl.gov> wrote:
> >From what I understand Barry doesn't want the threads to spin. > Lots of MPI calls spin because it's MUCH lower latency. Unless we have more threads than cores, what is the problem? > Also, synchronizing through an unguarded memory location seems to create a > race conditions. > Not if writes are atomic. There is always a way to do atomic writes (usually machine-word) because otherwise the operating system could not implement synchronization primitives. Isn't cmpxchg instruction-set specific? > All instruction sets have some analogue of cmpxchg because it's the building block for all other primitives. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.mcs.anl.gov/pipermail/petsc-dev/attachments/20111129/5c31198d/attachment.html>