Per code review:
- Main loop in the pixman_fill_buff16_mips routine now uses 4-byte writes
- Added alignment check to ensure that we don't encounter unaligned write
with the sw instruction (pixman_fill_buff16_mips)
- Added lowlevel-blt-bench results (src_n_0565/src_n_8888) in the log message.
Benchmark results (lowlevel-blt-bench) on Malta board (@1Ghz):
Referent:
src_n_0565 = L1: 238.14 L2: 233.15 M: 57.88 ( 77.23%) HT:
53.22 VT: 49.99 R: 47.73 RT: 24.79 ( 91Kops/s)
src_n_8888 = L1: 190.19 L2: 187.57 M: 28.94 ( 77.23%) HT:
27.91 VT: 27.33 R: 26.64 RT: 14.68 ( 77Kops/s)
Previous commit (with the 2-byte stores for pixman_fill_buff16_mips):
src_n_0565 = L1: 718.59 L2: 245.10 M:236.82 (315.64%) HT:
58.08 VT: 52.38 R: 51.62 RT: 24.56 ( 90Kops/s)
src_n_8888 = L1: 694.35 L2: 113.36 M:133.68 (356.36%) HT:
39.00 VT: 37.14 R: 34.88 RT: 15.77 ( 79Kops/s)
Optimized (with the 4-byte stores for pixman_fill_buff16_mips)
src_n_0565 = L1:1081.39 L2: 258.22 M:189.59 (252.91%) HT:
60.23 VT: 55.01 R: 53.44 RT: 23.68 ( 89Kops/s)
src_n_8888 = L1: 653.46 L2: 113.55 M:135.26 (360.86%) HT:
38.99 VT: 37.38 R: 34.95 RT: 18.67 ( 84Kops/s)
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