Author: arekm Date: Tue Oct 18 12:39:07 2011 GMT
Module: packages Tag: HEAD
---- Log message:
- from lkml
---- Files affected:
packages/kernel:
patch-3.0.6-7 (NONE -> 1.1) (NEW)
---- Diffs:
================================================================
Index: packages/kernel/patch-3.0.6-7
diff -u /dev/null packages/kernel/patch-3.0.6-7:1.1
--- /dev/null Tue Oct 18 14:39:07 2011
+++ packages/kernel/patch-3.0.6-7 Tue Oct 18 14:39:02 2011
@@ -0,0 +1,1413 @@
+diff --git a/Makefile b/Makefile
+index 7767a64..11c4249 100644
+--- a/Makefile
++++ b/Makefile
+@@ -1,6 +1,6 @@
+ VERSION = 3
+ PATCHLEVEL = 0
+-SUBLEVEL = 6
++SUBLEVEL = 7
+ EXTRAVERSION =
+ NAME = Sneaky Weasel
+
+diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
+index f8b9392..9a9706c 100644
+--- a/arch/arm/mach-ux500/Kconfig
++++ b/arch/arm/mach-ux500/Kconfig
+@@ -6,6 +6,7 @@ config UX500_SOC_COMMON
+ select ARM_GIC
+ select HAS_MTU
+ select ARM_ERRATA_753970
++ select ARM_ERRATA_754322
+
+ menu "Ux500 SoC"
+
+diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
+index 73031f7..4397972 100644
+--- a/arch/mips/jz4740/gpio.c
++++ b/arch/mips/jz4740/gpio.c
+@@ -18,7 +18,7 @@
+ #include <linux/init.h>
+
+ #include <linux/spinlock.h>
+-#include <linux/sysdev.h>
++#include <linux/syscore_ops.h>
+ #include <linux/io.h>
+ #include <linux/gpio.h>
+ #include <linux/delay.h>
+@@ -86,7 +86,6 @@ struct jz_gpio_chip {
+ spinlock_t lock;
+
+ struct gpio_chip gpio_chip;
+- struct sys_device sysdev;
+ };
+
+ static struct jz_gpio_chip jz4740_gpio_chips[];
+@@ -459,49 +458,47 @@ static struct jz_gpio_chip jz4740_gpio_chips[] = {
+ JZ4740_GPIO_CHIP(D),
+ };
+
+-static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
++static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
+ {
+- return container_of(dev, struct jz_gpio_chip, sysdev);
++ chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
++ writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
++ writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+ }
+
+-static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
++static int jz4740_gpio_suspend(void)
+ {
+- struct jz_gpio_chip *chip = sysdev_to_chip(dev);
++ int i;
+
+- chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
+- writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
+- writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
++ for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
++ jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
+
+ return 0;
+ }
+
+-static int jz4740_gpio_resume(struct sys_device *dev)
++static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
+ {
+- struct jz_gpio_chip *chip = sysdev_to_chip(dev);
+ uint32_t mask = chip->suspend_mask;
+
+ writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+ writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
++}
+
+- return 0;
++static void jz4740_gpio_resume(void)
++{
++ int i;
++
++ for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
++ jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
+ }
+
+-static struct sysdev_class jz4740_gpio_sysdev_class = {
+- .name = "gpio",
++static struct syscore_ops jz4740_gpio_syscore_ops = {
+ .suspend = jz4740_gpio_suspend,
+ .resume = jz4740_gpio_resume,
+ };
+
+-static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
++static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
+ {
+- int ret, irq;
+-
+- chip->sysdev.id = id;
+- chip->sysdev.cls = &jz4740_gpio_sysdev_class;
+- ret = sysdev_register(&chip->sysdev);
+-
+- if (ret)
+- return ret;
++ int irq;
+
+ spin_lock_init(&chip->lock);
+
+@@ -519,22 +516,17 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip
*chip, unsigned int id)
+ irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
+ handle_level_irq);
+ }
+-
+- return 0;
+ }
+
+ static int __init jz4740_gpio_init(void)
+ {
+ unsigned int i;
+- int ret;
+-
+- ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
+- if (ret)
+- return ret;
+
+ for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
+ jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
+
++ register_syscore_ops(&jz4740_gpio_syscore_ops);
++
+ printk(KERN_INFO "JZ4740 GPIO initialized\n");
+
+ return 0;
+diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
+index 581531d..8e073d8 100644
+--- a/arch/sparc/mm/init_64.c
++++ b/arch/sparc/mm/init_64.c
+@@ -511,6 +511,11 @@ static void __init read_obp_translations(void)
+ for (i = 0; i < prom_trans_ents; i++)
+ prom_trans[i].data &= ~0x0003fe0000000000UL;
+ }
++
++ /* Force execute bit on. */
++ for (i = 0; i < prom_trans_ents; i++)
++ prom_trans[i].data |= (tlb_type == hypervisor ?
++ _PAGE_EXEC_4V : _PAGE_EXEC_4U);
+ }
+
+ static void __init hypervisor_tlb_lock(unsigned long vaddr,
+diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
+index 68c3c13..50b3f14 100644
+--- a/arch/x86/pci/acpi.c
++++ b/arch/x86/pci/acpi.c
+@@ -43,6 +43,17 @@ static const struct dmi_system_id pci_use_crs_table[]
__initconst = {
+ DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
+ },
+ },
++ /* https://bugzilla.kernel.org/show_bug.cgi?id=30552 */
++ /* 2006 AMD HT/VIA system with two host bridges */
++ {
++ .callback = set_use_crs,
++ .ident = "ASUS M2V-MX SE",
++ .matches = {
++ DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
++ DMI_MATCH(DMI_BOARD_NAME, "M2V-MX SE"),
++ DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
++ },
++ },
+ {}
+ };
+
+diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
+index cab6960..1e9ab9b 100644
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -812,6 +812,18 @@ static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
+ DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
+ },
+ },
++ /*
++ * All BIOS versions for the Asus M3A support 64bit DMA.
++ * (all release versions from 0301 to 1206 were tested)
++ */
++ {
++ .ident = "ASUS M3A",
++ .matches = {
++ DMI_MATCH(DMI_BOARD_VENDOR,
++ "ASUSTeK Computer INC."),
++ DMI_MATCH(DMI_BOARD_NAME, "M3A"),
++ },
++ },
+ { }
+ };
+ const struct dmi_system_id *match;
+diff --git a/drivers/gpu/drm/radeon/atombios_dp.c
b/drivers/gpu/drm/radeon/atombios_dp.c
+index 7ad43c6..79e8ebc 100644
+--- a/drivers/gpu/drm/radeon/atombios_dp.c
++++ b/drivers/gpu/drm/radeon/atombios_dp.c
+@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct
radeon_connector *radeon_connector,
+ u8 msg[20];
+ int msg_bytes = send_bytes + 4;
+ u8 ack;
++ unsigned retry;
+
+ if (send_bytes > 16)
+ return -1;
+@@ -125,20 +126,22 @@ static int radeon_dp_aux_native_write(struct
radeon_connector *radeon_connector,
+ msg[3] = (msg_bytes << 4) | (send_bytes - 1);
+ memcpy(&msg[4], send, send_bytes);
+
+- while (1) {
++ for (retry = 0; retry < 4; retry++) {
+ ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
+ msg, msg_bytes, NULL, 0, delay,
&ack);
+- if (ret < 0)
++ if (ret == -EBUSY)
++ continue;
++ else if (ret < 0)
+ return ret;
+ if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
+- break;
++ return send_bytes;
+ else if ((ack & AUX_NATIVE_REPLY_MASK) ==
AUX_NATIVE_REPLY_DEFER)
+ udelay(400);
+ else
+ return -EIO;
+ }
+
+- return send_bytes;
++ return -EIO;
+ }
+
+ static int radeon_dp_aux_native_read(struct radeon_connector
*radeon_connector,
+@@ -149,26 +152,31 @@ static int radeon_dp_aux_native_read(struct
radeon_connector *radeon_connector,
+ int msg_bytes = 4;
+ u8 ack;
+ int ret;
++ unsigned retry;
+
+ msg[0] = address;
+ msg[1] = address >> 8;
+ msg[2] = AUX_NATIVE_READ << 4;
+ msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
+
+- while (1) {
++ for (retry = 0; retry < 4; retry++) {
+ ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
+ msg, msg_bytes, recv, recv_bytes,
delay, &ack);
+- if (ret == 0)
+- return -EPROTO;
+- if (ret < 0)
++ if (ret == -EBUSY)
++ continue;
++ else if (ret < 0)
+ return ret;
+ if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
+ return ret;
+ else if ((ack & AUX_NATIVE_REPLY_MASK) ==
AUX_NATIVE_REPLY_DEFER)
+ udelay(400);
++ else if (ret == 0)
++ return -EPROTO;
+ else
+ return -EIO;
+ }
++
++ return -EIO;
+ }
+
+ static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
+@@ -232,7 +240,9 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int
mode,
+ for (retry = 0; retry < 4; retry++) {
+ ret = radeon_process_aux_ch(auxch,
+ msg, msg_bytes, reply, reply_bytes,
0, &ack);
+- if (ret < 0) {
++ if (ret == -EBUSY)
++ continue;
++ else if (ret < 0) {
+ DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
+ return ret;
+ }
+diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
+index c975581..ea7a24e 100644
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -1593,48 +1593,6 @@ static u32
evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
+ return backend_map;
+ }
+
+-static void evergreen_program_channel_remap(struct radeon_device *rdev)
+-{
+- u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
+-
+- tmp = RREG32(MC_SHARED_CHMAP);
+- switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+- case 0:
+- case 1:
+- case 2:
+- case 3:
+- default:
+- /* default mapping */
+- mc_shared_chremap = 0x00fac688;
+- break;
+- }
+-
+- switch (rdev->family) {
+- case CHIP_HEMLOCK:
+- case CHIP_CYPRESS:
+- case CHIP_BARTS:
+- tcp_chan_steer_lo = 0x54763210;
+- tcp_chan_steer_hi = 0x0000ba98;
+- break;
+- case CHIP_JUNIPER:
+- case CHIP_REDWOOD:
+- case CHIP_CEDAR:
+- case CHIP_PALM:
+- case CHIP_SUMO:
+- case CHIP_SUMO2:
+- case CHIP_TURKS:
+- case CHIP_CAICOS:
+- default:
+- tcp_chan_steer_lo = 0x76543210;
+- tcp_chan_steer_hi = 0x0000ba98;
+- break;
+- }
+-
+- WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
+- WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
+- WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
+-}
+-
+ static void evergreen_gpu_init(struct radeon_device *rdev)
+ {
+ u32 cc_rb_backend_disable = 0;
+@@ -2080,8 +2038,6 @@ static void evergreen_gpu_init(struct radeon_device
*rdev)
+ WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+ WREG32(HDP_ADDR_CONFIG, gb_addr_config);
+
+- evergreen_program_channel_remap(rdev);
+-
+ num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3))
>> 12) + 1;
+ grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
+
+diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
+index 0b132a3..0c460c4 100644
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct
radeon_device *rdev,
+ return backend_map;
+ }
+
+-static void cayman_program_channel_remap(struct radeon_device *rdev)
+-{
+- u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
+-
+- tmp = RREG32(MC_SHARED_CHMAP);
+- switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+- case 0:
+- case 1:
+- case 2:
+- case 3:
+- default:
+- /* default mapping */
+- mc_shared_chremap = 0x00fac688;
+- break;
+- }
+-
+- switch (rdev->family) {
+- case CHIP_CAYMAN:
+- default:
+- //tcp_chan_steer_lo = 0x54763210
+- tcp_chan_steer_lo = 0x76543210;
+- tcp_chan_steer_hi = 0x0000ba98;
+- break;
+- }
+-
+- WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
+- WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
+- WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
+-}
+-
+ static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
+ u32 disable_mask_per_se,
+ u32 max_disable_mask_per_se,
+@@ -841,8 +811,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
+ WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+ WREG32(HDP_ADDR_CONFIG, gb_addr_config);
+
+- cayman_program_channel_remap(rdev);
+-
+ /* primary versions */
+ WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+ WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
+index d1b36f8..05b8b2c 100644
+--- a/drivers/gpu/drm/radeon/radeon_connectors.c
++++ b/drivers/gpu/drm/radeon/radeon_connectors.c
+@@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector
*connector)
+ if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+ int saved_dpms = connector->dpms;
+
+- if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
+- radeon_dp_needs_link_train(radeon_connector))
+- drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
+- else
++ /* Only turn off the display it it's physically disconnected */
++ if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
+ drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
++ else if (radeon_dp_needs_link_train(radeon_connector))
++ drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
+ connector->dpms = saved_dpms;
+ }
+ }
+diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c
b/drivers/gpu/drm/radeon/radeon_cursor.c
+index 3189a7e..f59a682 100644
+--- a/drivers/gpu/drm/radeon/radeon_cursor.c
++++ b/drivers/gpu/drm/radeon/radeon_cursor.c
+@@ -208,6 +208,13 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
+ int xorigin = 0, yorigin = 0;
+ int w = radeon_crtc->cursor_width;
+
++ if (ASIC_IS_AVIVO(rdev)) {
++ /* avivo cursor are offset into the total surface */
++ x += crtc->x;
++ y += crtc->y;
++ }
++ DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
++
+ if (x < 0)
+ xorigin = -x + 1;
+ if (y < 0)
+@@ -221,11 +228,6 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
+ int i = 0;
+ struct drm_crtc *crtc_p;
+
+- /* avivo cursor are offset into the total surface */
+- x += crtc->x;
+- y += crtc->y;
+- DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x,
crtc->y);
+-
+ /* avivo cursor image can't end on 128 pixel boundary or
+ * go past the end of the frame if both crtcs are enabled
+ */
+diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
+index 13690f3..8a171b2 100644
+--- a/drivers/gpu/drm/radeon/radeon_encoders.c
++++ b/drivers/gpu/drm/radeon/radeon_encoders.c
+@@ -1755,9 +1755,12 @@ static int radeon_atom_pick_dig_encoder(struct
drm_encoder *encoder)
+ /* DCE4/5 */
+ if (ASIC_IS_DCE4(rdev)) {
+ dig = radeon_encoder->enc_priv;
+- if (ASIC_IS_DCE41(rdev))
+- return radeon_crtc->crtc_id;
+- else {
++ if (ASIC_IS_DCE41(rdev)) {
++ if (dig->linkb)
++ return 1;
++ else
++ return 0;
++ } else {
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ if (dig->linkb)
+diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
+index 4de5189..f2516e6 100644
+--- a/drivers/gpu/drm/radeon/rv770.c
++++ b/drivers/gpu/drm/radeon/rv770.c
+@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct
radeon_device *rdev,
+ return backend_map;
+ }
+
+-static void rv770_program_channel_remap(struct radeon_device *rdev)
+-{
+- u32 tcp_chan_steer, mc_shared_chremap, tmp;
+- bool force_no_swizzle;
+-
+- switch (rdev->family) {
+- case CHIP_RV770:
+- case CHIP_RV730:
+- force_no_swizzle = false;
+- break;
+- case CHIP_RV710:
+- case CHIP_RV740:
+- default:
+- force_no_swizzle = true;
+- break;
+- }
+-
+- tmp = RREG32(MC_SHARED_CHMAP);
+- switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+- case 0:
+- case 1:
+- default:
+- /* default mapping */
+- mc_shared_chremap = 0x00fac688;
+- break;
+- case 2:
+- case 3:
+- if (force_no_swizzle)
+- mc_shared_chremap = 0x00fac688;
+- else
+- mc_shared_chremap = 0x00bbc298;
+- break;
+- }
+-
+- if (rdev->family == CHIP_RV740)
+- tcp_chan_steer = 0x00ef2a60;
+- else
+- tcp_chan_steer = 0x00fac688;
+-
+- /* RV770 CE has special chremap setup */
+- if (rdev->pdev->device == 0x944e) {
+- tcp_chan_steer = 0x00b08b08;
+- mc_shared_chremap = 0x00b08b08;
+- }
+-
+- WREG32(TCP_CHAN_STEER, tcp_chan_steer);
+- WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
+-}
+-
+ static void rv770_gpu_init(struct radeon_device *rdev)
+ {
+ int i, j, num_qd_pipes;
+@@ -784,8 +735,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
+ WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
+ WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
+
+- rv770_program_channel_remap(rdev);
+-
+ WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+ WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+ WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+diff --git a/drivers/ide/ide-disk.c b/drivers/ide/ide-disk.c
+index 2747980..16f69be 100644
+--- a/drivers/ide/ide-disk.c
++++ b/drivers/ide/ide-disk.c
+@@ -435,7 +435,12 @@ static int idedisk_prep_fn(struct request_queue *q,
struct request *rq)
+ if (!(rq->cmd_flags & REQ_FLUSH))
+ return BLKPREP_OK;
+
+- cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
++ if (rq->special) {
++ cmd = rq->special;
++ memset(cmd, 0, sizeof(*cmd));
++ } else {
++ cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
++ }
+
+ /* FIXME: map struct ide_taskfile on rq->cmd[] */
+ BUG_ON(cmd == NULL);
+diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c
+index 451c3bb..ebdae6e 100644
+--- a/drivers/md/dm-table.c
++++ b/drivers/md/dm-table.c
+@@ -1184,14 +1184,15 @@ static void dm_table_set_integrity(struct dm_table *t)
+ return;
+
+ template_disk = dm_table_get_integrity_disk(t, true);
+- if (!template_disk &&
+- blk_integrity_is_initialized(dm_disk(t->md))) {
++ if (template_disk)
++ blk_integrity_register(dm_disk(t->md),
++ blk_get_integrity(template_disk));
++ else if (blk_integrity_is_initialized(dm_disk(t->md)))
+ DMWARN("%s: device no longer has a valid integrity profile",
+ dm_device_name(t->md));
+- return;
+- }
+- blk_integrity_register(dm_disk(t->md),
+- blk_get_integrity(template_disk));
++ else
++ DMWARN("%s: unable to establish an integrity profile",
++ dm_device_name(t->md));
+ }
+
+ void dm_table_set_restrictions(struct dm_table *t, struct request_queue *q,
+diff --git a/drivers/md/md.c b/drivers/md/md.c
+index 8554082..bc83428 100644
+--- a/drivers/md/md.c
++++ b/drivers/md/md.c
+@@ -61,6 +61,11 @@
+ static void autostart_arrays(int part);
+ #endif
+
++/* pers_list is a list of registered personalities protected
++ * by pers_lock.
<<Diff was trimmed, longer than 597 lines>>
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