On 2026/07/23 10:35, Stuart Henderson wrote: > On 2026/07/17 15:18, Thomas Dettbarn wrote: > > Hello. > > > > A couple of days ago, yosys 0.67 was release, so I took the liberty to > > update my collection of ports related to FPGA design. > > Please find my latest update to my port for cad/nextpnr attached > > to this email. > > > > Thomas > > same nitpicking with license marker as prjpeppercorn, otherwise ok
oh, and drop the empty line after .include at the end
