At 05:06 PM 4/10/01 -0600, Gladieux, Jed wrote:
>Does anyone know how to create new design rules. For example, I would like
>to flag instances where component outlines on the silkscreen layers overlap.
[using Protel 98]
Component interference rules did not exist in Protel 98. They've been added
to Protel 99SE, though they could still use improvement. They assume a
bounding rectangle being the extent of the primitives on all layers (don't
ask me what happens if the component is rotated -- I haven't checked). If
you have component outlines at MMC, you will get over-conservative spacing.
I think we would prefer a polygon outline on a defined layer, and the
polygon outline track would have zero dimension; one should be able to butt
them up against each other without creating an error, if clearance is set
to zero. Any crossing of polygon outlines would create an error. There's a
fairly simple algorithm for detecting these crossings....
I suppose it doesn't have to be a polygon, it could be discrete tracks.
Ultimately, we will want height information in there. For example, one
might tuck a resistor underneath the curve of a large axial electrolytic
capacitor without creating any assembly problem, since the axial cap will
be inserted last anyway. When the 3-D analyzer is ready for prime time,
with accessible models, I'd think full component clearance checking will
become possible. But just having polygon outlines would be a great start.
[EMAIL PROTECTED]
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433
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