At 07:57 AM 1/31/2002 -0800, Peter Bennett wrote: >Looking closely at the schematics, it seems I wasn't consistent with the >order on one bus, and Protel still made the right connections. On the >processor schematic, I use AD[0..7], but the project sheet and the sheet >containing the destination of the bus use AD[7..0]. Despite this, AD0 >connects to the right pins at both ends!
Right. That is now what I would expect. It doesn't matter what sequence you place individual net labels, and all that a bus label does is to reference a series of net labels. Once we know that it knows that AD[7..0] references AD7, AD6, AD5, ... AD0, we should be confident that it will netlist the same as AD[0..7]. The potential bug would have been that the first number was incremented until it reached the second number. The programmers, however, recognised that they should decrement if the second number was smaller than the first. In other words, they got it right. Bus/Port/Sheet Entry label Wish list: AD[0, 3..7] i.e., AD1 and 2 are not included similarly, something like CONTROL[/RD,/WR,/ALE] would occasionally be useful. This would link nets /RD,/WR,/ALE. If an item in the list was not a number, it would not be prefixed. CONTROL[0..2,/RD] would resolve to CONTROL0, CONTROL1, CONTROL2, /RD. I think the meaning of these is pretty obvious. It should likewise be obvious to the program. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
