At 17:30 14.01.2004 -0500, you wrote:
At 02:06 AM 1/14/2004, Juha Pajunen wrote:
Pleace see this file:
http://groups.yahoo.com/group/protel-users/files/junk/PLANE_ERROR.jpg

You are seeing a composite display, not just the plane. You can tell because, inside one of the thermal reliefs, there is a square pad, which would be the multilayer or perhaps solder mask or other aspect of the pad which is not on the power plane. There would never be a square flash on a power plane unless you explicitly place it there as an independent primitive literally on the plane, generally not a good idea.


(If you need to place primitives on a power plane, almost always it would be better to place lines; but note that 99SE does not check planes for continuity. If you want continuity checking, you'd have to kludge it with a composite, it can be done.)

The other pad blowouts on the plane also show the pad itself.... On the true plane, you would only see a single round blowout for a pad not connected to the plane, or a thermal relief for a thermally relieved pad. If there is no thermal relief, you won't see *anything* on the plane itself for a via or pad direct-connected to the plane, though it is a good idea to have hole display enabled so you can tell what is going on.

The first thought was something is wrong with the pad stack. But there are component pads and also a free pad with the same behaviour (It is a pad in the lowwer right corener, isn't it?). Strange. Do you use pad stacks? Shouldn't have an influence on plane layers anyway.
Are you in the single layer mode or do you have the other layers dissabled (I don't think you are in single layer, because the net lines are invisible in this mode)?
Do you have a layer with the same colour than the plane (solder/paste mask)?


The net connectivity seems to be ok, because there are hair line crosses on the 3.3V pads and via.

Just some hints for hunting.

By the way, it appears you have vias thermally relieved. That is probably not the best practice, it is better to set a design rule so that all vias are direct-connect. Vias do not generally need thermal relief, and direct connection has the lowest impedance.

And also reduces problems with the non existent power plane continuity check.


Edi









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