Author: David Schneider <[email protected]>
Branch: arm-backend-2
Changeset: r45108:8fa59bf8aa58
Date: 2011-06-24 17:41 +0200
http://bitbucket.org/pypy/pypy/changeset/8fa59bf8aa58/
Log: implement support for sqrt in the ARM backend
diff --git a/pypy/jit/backend/arm/assembler.py
b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -703,7 +703,8 @@
regalloc.prepare_force_spill(op, fcond)
else:
arglocs = regalloc.operations[opnum](regalloc, op, fcond)
- fcond = self.operations[opnum](self, op, arglocs, regalloc,
fcond)
+ if arglocs is not None:
+ fcond = self.operations[opnum](self, op, arglocs,
regalloc, fcond)
if op.result:
regalloc.possibly_free_var(op.result)
regalloc.possibly_free_vars_for_op(op)
diff --git a/pypy/jit/backend/arm/instructions.py
b/pypy/jit/backend/arm/instructions.py
--- a/pypy/jit/backend/arm/instructions.py
+++ b/pypy/jit/backend/arm/instructions.py
@@ -129,12 +129,13 @@
# based on encoding from A7.5 VFP data-processing instructions
# opc2 is one of the parameters and therefore ignored here
float64_data_proc_instructions = {
- 'VADD' : {'opc1':0x3, 'opc3':0x0},
- 'VSUB' : {'opc1':0x3, 'opc3':0x1},
- 'VMUL' : {'opc1':0x2, 'opc3':0x0},
- 'VDIV' : {'opc1':0x8, 'opc3':0x0},
- 'VCMP' : {'opc1':0xB, 'opc2':0x4, 'opc3':0x1, 'result': False},
- 'VNEG' : {'opc1':0xB, 'opc2':0x1, 'opc3':0x1, 'base': False},
- 'VABS' : {'opc1':0xB, 'opc2':0x0, 'opc3':0x3, 'base': False},
+ 'VADD' : {'opc1':0x3, 'opc3':0x0},
+ 'VSUB' : {'opc1':0x3, 'opc3':0x1},
+ 'VMUL' : {'opc1':0x2, 'opc3':0x0},
+ 'VDIV' : {'opc1':0x8, 'opc3':0x0},
+ 'VCMP' : {'opc1':0xB, 'opc2':0x4, 'opc3':0x1, 'result': False},
+ 'VNEG' : {'opc1':0xB, 'opc2':0x1, 'opc3':0x1, 'base': False},
+ 'VABS' : {'opc1':0xB, 'opc2':0x0, 'opc3':0x3, 'base': False},
+ 'VSQRT' : {'opc1':0xB, 'opc2':0x1, 'opc3':0x3, 'base': False},
#'VCVT' : {'opc1':0xB, 'opc2':0xE, 'opc3':0x1, 'base': False},
}
diff --git a/pypy/jit/backend/arm/opassembler.py
b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -986,6 +986,7 @@
emit_op_float_neg = gen_emit_unary_float_op('VNEG')
emit_op_float_abs = gen_emit_unary_float_op('VABS')
+ emit_op_math_sqrt = gen_emit_unary_float_op('VSQRT')
emit_op_float_lt = gen_emit_float_cmp_op(c.VFP_LT)
emit_op_float_le = gen_emit_float_cmp_op(c.VFP_LE)
diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -21,6 +21,7 @@
from pypy.jit.backend.llsupport import symbolic
from pypy.rpython.lltypesystem import lltype, rffi, rstr, llmemory
from pypy.jit.codewriter import heaptracker
+from pypy.jit.codewriter.effectinfo import EffectInfo
from pypy.rlib.objectmodel import we_are_translated
class TempInt(TempBox):
@@ -442,6 +443,14 @@
prepare_op_int_invert = prepare_op_int_neg
def prepare_op_call(self, op, fcond):
+ effectinfo = op.getdescr().get_extra_info()
+ if effectinfo is not None:
+ oopspecindex = effectinfo.oopspecindex
+ if oopspecindex == EffectInfo.OS_MATH_SQRT:
+ args = self.prepare_op_math_sqrt(op, fcond)
+ self.assembler.emit_op_math_sqrt(op, args, self, fcond)
+ return
+ self._consider_call(op)
args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
return args
@@ -1047,6 +1056,13 @@
prepare_op_float_neg = prepare_float_op(base=False)
prepare_op_float_abs = prepare_float_op(base=False)
+ def prepare_op_math_sqrt(self, op, fcond):
+ loc, box = self._ensure_value_is_boxed(op.getarg(1))
+ self.possibly_free_var(box)
+ res = self.vfprm.force_allocate_reg(op.result)
+ self.possibly_free_var(op.result)
+ return [loc, res]
+
def prepare_op_cast_float_to_int(self, op, fcond):
locs = []
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