Author: hager <sven.ha...@uni-duesseldorf.de>
Branch: ppc-jit-backend
Changeset: r46463:14556413a5ed
Date: 2011-08-12 11:36 +0200
http://bitbucket.org/pypy/pypy/changeset/14556413a5ed/

Log:    Beautified emit_int_add and emit_int_sub, fixed a bug in
        emit_int_sub regarding BoxInt and ConstInt.

diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py 
b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
@@ -928,20 +928,14 @@
         arg1 = op.getarg(1)
         if isinstance(arg0, BoxInt):
             regnum = cpu.reg_map[arg0]
-            if isinstance(arg1, ConstInt):
-                self.addi(cpu.next_free_register, regnum, arg1.value)
-            elif isinstance(arg1, BoxInt):
-                regnum2 = cpu.reg_map[arg1]
-                self.add(cpu.next_free_register, regnum, regnum2)
         else:
             regnum = cpu.get_next_register()
             self.load_word(regnum, arg0.value)
-            if isinstance(arg1, ConstInt):
-                self.addi(cpu.next_free_register, regnum, arg1.value)
-            elif isinstance(arg1, BoxInt):
-                regnum2 = cpu.reg_map[arg1]
-                self.add(cpu.next_free_register, regnum, regnum2)
-            
+        if isinstance(arg1, ConstInt):
+            self.addi(cpu.next_free_register, regnum, arg1.value)
+        elif isinstance(arg1, BoxInt):
+            regnum2 = cpu.reg_map[arg1]
+            self.add(cpu.next_free_register, regnum, regnum2)
         result = op.result
         cpu.reg_map[result] = cpu.next_free_register
         cpu.next_free_register += 1
@@ -949,9 +943,13 @@
     def emit_int_sub(self, op, cpu):
         arg0 = op.getarg(0)
         arg1 = op.getarg(1)
-        regnum = cpu.reg_map[arg0]
+        if isinstance(arg0, BoxInt):
+            regnum = cpu.reg_map[arg0]
+        else:
+            regnum = cpu.get_next_register()
+            self.load_word(regnum, arg0.value)
         if isinstance(arg1, ConstInt):
-            self.addi(cpu.next_free_register, regnum, -arg1.value)
+            self.subi(cpu.next_free_register, regnum, arg1.value)
         elif isinstance(arg1, BoxInt):
             regnum2 = cpu.reg_map[arg1]
             self.sub(cpu.next_free_register, regnum, regnum2)
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