Author: edelsohn
Branch: ppc-jit-backend
Changeset: r46711:448d8da161a4
Date: 2011-08-22 21:41 -0400
http://bitbucket.org/pypy/pypy/changeset/448d8da161a4/
Log: emit_int_le, emit_int_lt, emit_int_gt, emit_int_ge PPC64 cmpd
emit_int_ne fix typo
diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
@@ -1109,27 +1109,39 @@
self.srdi(free_reg, free_reg, 6)
def emit_int_le(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.cror(31, 30, 28)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 0, 31, 31)
def emit_int_lt(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 29, 31, 31)
def emit_int_ne(self, op, cpu, reg0, reg1, free_reg):
- self.emit_int_eq(self, op, cpu, reg0, reg1, free_reg)
+ self.emit_int_eq(op, cpu, reg0, reg1, free_reg)
self.xori(free_reg, free_reg, 1)
def emit_int_gt(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 30, 31, 31)
def emit_int_ge(self, op, cpu, reg0, reg1, free_reg):
- self.cmpw(7, reg0, reg1)
+ if IS_PPC_32:
+ self.cmpw(7, reg0, reg1)
+ else:
+ self.cmpd(7, reg0, reg1)
self.cror(31, 30, 29)
self.mfcr(free_reg)
self.rlwinm(free_reg, free_reg, 0, 31, 31)
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