Author: Armin Rigo <ar...@tunes.org>
Branch:
Changeset: r71086:10ad80d9a210
Date: 2014-04-30 14:53 +0200
http://bitbucket.org/pypy/pypy/changeset/10ad80d9a210/
Log: Finally clean up this small mess: replace MOVD with MOVDQ or MOVD32.
The latter is always 32-bit. The former is always WORD-sized and
corresponds to either MOVD or MOVQ from the Intel documentation.
Fixes 9761ff01220d.
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -1173,13 +1173,13 @@
self.mc.CVTSD2SS(loctmp, loc0)
assert isinstance(resloc, RegLoc)
assert isinstance(loctmp, RegLoc)
- self.mc.MOVD_rx(resloc.value, loctmp.value)
+ self.mc.MOVD32_rx(resloc.value, loctmp.value)
def genop_cast_singlefloat_to_float(self, op, arglocs, resloc):
loc0, = arglocs
assert isinstance(resloc, RegLoc)
assert isinstance(loc0, RegLoc)
- self.mc.MOVD_xr(resloc.value, loc0.value)
+ self.mc.MOVD32_xr(resloc.value, loc0.value)
self.mc.CVTSS2SD_xx(resloc.value, resloc.value)
def genop_convert_float_bytes_to_longlong(self, op, arglocs, resloc):
@@ -1187,7 +1187,7 @@
if longlong.is_64_bit:
assert isinstance(resloc, RegLoc)
assert isinstance(loc0, RegLoc)
- self.mc.MOVD(resloc, loc0)
+ self.mc.MOVDQ(resloc, loc0)
else:
self.mov(loc0, resloc)
@@ -1196,7 +1196,7 @@
if longlong.is_64_bit:
assert isinstance(resloc, RegLoc)
assert isinstance(loc0, RegLoc)
- self.mc.MOVD(resloc, loc0)
+ self.mc.MOVDQ(resloc, loc0)
else:
self.mov(loc0, resloc)
@@ -1262,7 +1262,7 @@
loc = arglocs[0]
assert isinstance(resloc, RegLoc)
if isinstance(loc, RegLoc):
- self.mc.MOVD_rx(resloc.value, loc.value)
+ self.mc.MOVD32_rx(resloc.value, loc.value)
elif isinstance(loc, FrameLoc):
self.mc.MOV_rb(resloc.value, loc.value)
else:
@@ -1277,16 +1277,16 @@
assert isinstance(loc1, RegLoc)
assert isinstance(loc2, RegLoc)
assert isinstance(resloc, RegLoc)
- self.mc.MOVD_xr(loc2.value, loc1.value)
+ self.mc.MOVD32_xr(loc2.value, loc1.value)
self.mc.PSRAD_xi(loc2.value, 31) # -> 0 or -1
- self.mc.MOVD_xr(resloc.value, loc1.value)
+ self.mc.MOVD32_xr(resloc.value, loc1.value)
self.mc.PUNPCKLDQ_xx(resloc.value, loc2.value)
def genop_llong_from_uint(self, op, arglocs, resloc):
loc1, = arglocs
assert isinstance(resloc, RegLoc)
assert isinstance(loc1, RegLoc)
- self.mc.MOVD_xr(resloc.value, loc1.value)
+ self.mc.MOVD32_xr(resloc.value, loc1.value)
def genop_llong_eq(self, op, arglocs, resloc):
loc1, loc2, locxtmp = arglocs
@@ -1571,8 +1571,8 @@
self.mc.OR_rr(edx.value, eax.value)
else:
loc1, = arglocs
- self.mc.MOVD_xr(loc1.value, edx.value)
- self.mc.MOVD_xr(resloc.value, eax.value)
+ self.mc.MOVD32_xr(loc1.value, edx.value)
+ self.mc.MOVD32_xr(resloc.value, eax.value)
self.mc.PUNPCKLDQ_xx(resloc.value, loc1.value)
def genop_guard_guard_true(self, ign_1, guard_op, guard_token, locs,
ign_2):
diff --git a/rpython/jit/backend/x86/callbuilder.py
b/rpython/jit/backend/x86/callbuilder.py
--- a/rpython/jit/backend/x86/callbuilder.py
+++ b/rpython/jit/backend/x86/callbuilder.py
@@ -242,8 +242,8 @@
if self.tmpresloc is None:
if self.restype == 'L': # long long
# move eax/edx -> xmm0
- self.mc.MOVD_xr(resloc.value^1, edx.value)
- self.mc.MOVD_xr(resloc.value, eax.value)
+ self.mc.MOVD32_xr(resloc.value^1, edx.value)
+ self.mc.MOVD32_xr(resloc.value, eax.value)
self.mc.PUNPCKLDQ_xx(resloc.value, resloc.value^1)
else:
# float: we have to go via the stack
@@ -435,7 +435,7 @@
if isinstance(src, ImmedLoc):
self.mc.MOV(X86_64_SCRATCH_REG, src)
src = X86_64_SCRATCH_REG
- self.mc.MOVD(dst, src)
+ self.mc.MOVD32(dst, src)
# Finally remap the arguments in the main regs
remap_frame_layout(self.asm, src_locs, dst_locs, X86_64_SCRATCH_REG)
@@ -447,7 +447,7 @@
if self.restype == 'S' and self.tmpresloc is None:
# singlefloat return: use MOVD to load the target register
# from the lower 32 bits of XMM0
- self.mc.MOVD(self.resloc, xmm0)
+ self.mc.MOVD32(self.resloc, xmm0)
else:
CallBuilderX86.load_result(self)
@@ -469,7 +469,7 @@
if self.restype == 'S':
# singlefloat return: use MOVD to store the lower 32 bits
# of XMM0 into the tmpresloc (register or [ESP])
- self.mc.MOVD(self.tmpresloc, xmm0)
+ self.mc.MOVD32(self.tmpresloc, xmm0)
else:
assert self.restype == INT
self.mc.MOV(self.tmpresloc, eax)
diff --git a/rpython/jit/backend/x86/regloc.py
b/rpython/jit/backend/x86/regloc.py
--- a/rpython/jit/backend/x86/regloc.py
+++ b/rpython/jit/backend/x86/regloc.py
@@ -662,7 +662,8 @@
PXOR = _binaryop('PXOR')
PCMPEQD = _binaryop('PCMPEQD')
- MOVD = _binaryop('MOVD')
+ MOVDQ = _binaryop('MOVDQ')
+ MOVD32 = _binaryop('MOVD32')
CALL = _relative_unaryop('CALL')
JMP = _relative_unaryop('JMP')
diff --git a/rpython/jit/backend/x86/rx86.py b/rpython/jit/backend/x86/rx86.py
--- a/rpython/jit/backend/x86/rx86.py
+++ b/rpython/jit/backend/x86/rx86.py
@@ -617,12 +617,17 @@
CVTSS2SD_xb = xmminsn('\xF3', rex_nw, '\x0F\x5A',
register(1, 8), stack_bp(2))
- # These work on machine sized registers, so MOVD is actually MOVQ
- # when running on 64 bits. Note a bug in the Intel documentation:
+ # These work on machine sized registers, so "MOVDQ" is MOVD when running
+ # on 32 bits and MOVQ when running on 64 bits. "MOVD32" is always 32-bit.
+ # Note a bug in the Intel documentation:
# http://lists.gnu.org/archive/html/bug-binutils/2007-07/msg00095.html
- MOVD_rx = xmminsn('\x66', rex_w, '\x0F\x7E', register(2, 8), register(1),
'\xC0')
- MOVD_xr = xmminsn('\x66', rex_w, '\x0F\x6E', register(1, 8), register(2),
'\xC0')
- MOVD_xb = xmminsn('\x66', rex_w, '\x0F\x6E', register(1, 8), stack_bp(2))
+ MOVDQ_rx = xmminsn('\x66', rex_w, '\x0F\x7E', register(2, 8), register(1),
'\xC0')
+ MOVDQ_xr = xmminsn('\x66', rex_w, '\x0F\x6E', register(1, 8), register(2),
'\xC0')
+ MOVDQ_xb = xmminsn('\x66', rex_w, '\x0F\x6E', register(1, 8), stack_bp(2))
+
+ MOVD32_rx = xmminsn('\x66', rex_nw, '\x0F\x7E', register(2, 8),
register(1), '\xC0')
+ MOVD32_xr = xmminsn('\x66', rex_nw, '\x0F\x6E', register(1, 8),
register(2), '\xC0')
+ MOVD32_xb = xmminsn('\x66', rex_nw, '\x0F\x6E', register(1, 8),
stack_bp(2))
PSRAD_xi = xmminsn('\x66', rex_nw, '\x0F\x72', register(1), '\xE0',
immediate(2, 'b'))
diff --git a/rpython/jit/backend/x86/test/test_rx86_32_auto_encoding.py
b/rpython/jit/backend/x86/test/test_rx86_32_auto_encoding.py
--- a/rpython/jit/backend/x86/test/test_rx86_32_auto_encoding.py
+++ b/rpython/jit/backend/x86/test/test_rx86_32_auto_encoding.py
@@ -183,8 +183,11 @@
g = open(inputname, 'w')
g.write('\x09.string "%s"\n' % BEGIN_TAG)
#
- if instrname == 'MOVD' and self.WORD == 8:
- instrname = 'MOVQ'
+ if instrname == 'MOVDQ':
+ if self.WORD == 8:
+ instrname = 'MOVQ'
+ else:
+ instrname = 'MOVD'
if argmodes == 'xb':
py.test.skip('"as" uses an undocumented alternate encoding??')
#
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